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5- 10
MC68330 USER'S MANUAL
MOTOROLA
5.2.2 Registers
Registers D7 to D0 are used as data registers for bit, byte (8-bit), word (16-bit), long-word
(32-bit), and quad-word (64-bit) operations. Registers A6 to A0 and the USP and SSP are
address registers that may be used as software SPs or base address registers. Register
A7 (shown as A7 and A7' in Figures 5-3 and 5-4) is a register designation that applies to
the USP in the user privilege level and to the SSP in the supervisor privilege level. In
addition, address registers may be used for word and long-word operations. All of the 16
general-purpose registers (D7 to D0, A7 to A0) may be used as index registers.
The PC contains the address of the next instruction to be executed by the CPU32. During
instruction execution and exception processing, the processor automatically increments
the contents of the PC or places a new value in the PC, as appropriate.
The SR (see Figure 5-5) contains condition codes, an interrupt priority mask (three bits),
and three control bits. Condition codes reflect the results of a previous operation. The
codes are contained in the low byte (CCR) of the SR. The interrupt priority mask
determines the level of priority an interrupt must have in order to be acknowledged. The
control bits determine trace mode and privilege level. At user privilege level, only the CCR
is available. At supervisor privilege level, software can access the full SR.
The VBR contains the base address of the exception vector table in memory. The
displacement of an exception vector is added to the value in this register to access the
vector table.
Alternate function code registers (SFC and DFC) contain 3-bit function codes. The CPU32
generates a function code each time it accesses an address. Specific codes are assigned
to each type of access. The codes can be used to select eight dedicated 4G-byte address
spaces. The MOVE instructions can use registers SFC and DFC to specify the function
code of a memory address.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
T1
T0
S
0
I2I1I0
0
X
N
Z
V
C
EXTEND
NEGATIVE
ZERO
OVERFLOW
CARRY
INTERRUPT
PRIORITY MAS
SUPERVISOR/USE
STATE
TRACE
ENABLE
SYSTEM BYT
USER BYTE
(CONDITION CODE REGIST
Figure 5-5. Status Register