MOTOROLA
MC68330 USER’S MANUAL
3- 7
OP1
OP0
OP2
OP1
OP0
OP3
OP2
OP1
OP0
31
23
15
7
0
D0
D8
D15
D7
OP0
(OP0
OP0
(OP0
OP0
(OP1
(OP0
OP1
OP0
(OP1
OP0
(OP0
OP0
OP1
(OP0
OP0
(OP1
OP0
(OP0
OP0
OP1
(OP0
OP0
A0
SIZ0
SIZ1
Case
(a)
(b)
(c)
(d)
(e)
(g)
(f)
(h)
(i)
(j)
(k)
(l)
(m)
(n)
(o)
01
X
10
0100
X
0110
X
10010
10110
1000
X
1010
X
11010
11110
1100
X
1110
X
00010
00110
0000
X
0010
X
Transfer Ca
Byte to By
Byte to Word (Ev
Byte to Word (O
Word to Byte (Align
Word to Byte (Misalig
Word to Word (Alig
Word to Word (Misalig
3 Byte to Byte (Align
3 Byte to Byte (Misalig
3 Byte to Word (Align
3 Byte to Word (Misalig
Long Word to Byte (Alig
Long Word to Byte (Misalig
Long Word to Word (Ali
Long Word to Word (Misali
OPERAND
Data Bu
DSACK
NOTES:
1.Operands in parentheses are ignored by the MC68330 during read cycles.
2. Misaligned and 3 byte transfer cases, identified by an asterisk, are not supported by the MC68330.
3. A 3-byte to byte transfer does occur as the second byte transfer of a long-word to byte port transfer.
Figure 3-2. MC68330 Interface to Various Port Sizes
3.2.2 Misaligned Operands
In this architecture, the basic operand size is 16 bits. Operand misalignment refers to
whether an operand is aligned on a word boundary or overlaps the word boundary,
determined by address line A0. When A0 is low, the address is even and is a word and
byte boundary. When A0 is high, the address is odd and is a byte boundary only. A byte
operand is properly aligned at any address; a word or long-word operand is misaligned at
an odd address.
At most, each bus cycle can transfer a word of data aligned on a word boundary. If the
MC68330 transfers a long-word operand over a 16-bit port, the most significant operand
word is transferred on the first bus cycle, and the least significant operand word is
transferred on a following bus cycle.
The CPU32 restricts all operands (both data and instructions) to be aligned. That is, word
and long-word operands must be located on a word or long-word boundary, respectively.
The only type of transfer that can be performed to an odd address is a single-byte transfer,
referred to as an odd-byte transfer. If a misaligned access is attempted, the CPU32
generates an address error exception, and enters exception processing. Refer to Section
5 CPU32 for more information on exception processing.