![](http://datasheet.mmic.net.cn/90000/MC68330FC16_datasheet_3506366/MC68330FC16_177.png)
MOTOROLA
MC68330 USER'S MANUAL
5- 73
5.6.3.1 TYPES OF FAULTS. An efficient implementation of instruction restart dictates that
faults on some bus cycles be treated differently than faults on other bus cycles. The
CPU32 defines four fault types: released write faults, faults during exception processing,
faults during MOVEM operand transfer, and faults on any other bus cycle.
5.6.3.1.1 Type I — Released Write Faults. CPU32 instruction pipelining can cause a final
instruction write to overlap the execution of a following instruction. A write that is
overlapped is called a released write. Since the machine context for the instruction that
queued the write is lost as soon as the following instruction starts, it is impossible to restart
the faulted instruction.
Released write faults are taken at the next instruction boundary. The stacked PC is that of
the next unexecuted instruction. If a subsequent instruction attempts an operand access
while a released write fault is pending, the instruction is aborted and the write fault is
acknowledged. This action prevents stale data from being used by the instruction.
The SSW for a released write fault contains the following bit pattern:
15
14
13
12
11
10
98765432
0
000
TR
B1
B0
1000
LG
SIZ
FUNC
TR, B1, and B0 are set if the corresponding exception is pending when the BERR
exception is taken. Status regarding the faulted bus cycle is reflected in the SSW LG, SIZ,
and FUNC fields.
The remainder of the stack contains the PC of the next unexecuted instruction, the current
SR, the address of the faulted memory location, and the contents of the data buffer which
was to be written to memory. This data is written on the stack in the format depicted in
Figure 5-21.
5.6.3.1.2 Type II — Prefetch, Operand, RMW, and MOVEP Faults. The majority of
BERR exceptions are included in this category — all instruction prefetches, all operand
reads, all RMW cycles, and all operand accesses resulting from execution of MOVEP
(except the last write of a MOVEP Rn,
ea or the last write of MOVEM, which are type I
faults). The TAS, MOVEP, and MOVEM instructions account for all operand writes not
considered released.
All type II faults cause an immediate exception that aborts the current instruction. Any
registers that were altered as the result of an EA calculation (i.e., postincrement or
predecrement) are restored prior to processing the bus cycle fault.
The SSW for faults in this category contains the following bit pattern:
15
14
13
12
11
10
98765432
0
0000
B1
B0
0
RM
IN
RW
LG
SIZ
FUNC
The trace pending bit is always cleared, since the instruction will be restarted upon return
from the handler. Saving a pending exception on the stack causes a trace exception to be
taken prior to restarting the instruction. If the exception handler does not alter the stacked
SR trace bits, the trace is requeued when the instruction is started.