MOTOROLA
MC68330 USER'S MANUAL
5- 29
MC68000/MC68008/MC68010
ADDRESS EXTENSION WORD
15
14
12
11
10
9
8
7
0
D/A
REGISTER
W/L
0
DISPLACEMENT INTEGER
D/A:
0 = Data Register Select
1 = Address Register Select
W/L
0 = Word-Sized Operation
1 = Long-Word-Sized Operation
CPU32/MC68020
EXTENSION WORD
15
14
12
11
10
9
8
7
0
D/A
REGISTER
W/L
SCALE
0
DISPLACEMENT INTEGER
D/A:
0 = Data Register Select
1 = Address Register Select
W/L
0 = Word-Sized Operation
1 = Long-Word-Sized Operation
SCALE:
00 = Scale Factor 1 (Compatible with MC68000)
01 = Scale Factor 2 (Extension to MC68000)
10 = Scale Factor 4 (Extension to MC68000)
11 = Scale Factor 8 (Extension to MC68000)
Figure 5-14. M68000 Family Address Extension Words
5.3.7 Other Data Structures
In addition to supporting the array data structure with the index addressing mode, M68000
processors also support stack and queue data structures with the address register indirect
postincrement and predecrement addressing modes. A stack is a last-in-first-out (LIFO)
list; a queue is a first-in-first-out (FIFO) list. When data is added to a stack or queue, it is
pushed onto the structure; when it is removed, it is " popped'' or pulled from the structure.
The system stack is used implicitly by many instructions; user stacks and queues may be
created and maintained through use of addressing modes.
5.3.7.1 SYSTEM STACK. Address register 7 (A7) is the system SP. The SP is either the
SSP or the USP, depending on the state of the S-bit in the SR. If the S-bit indicates the
supervisor state, the SSP is the SP, and the USP cannot be referenced as an address
register. If the S-bit indicates the user state, the USP is the active SP, and the SSP cannot
be referenced. Each system stack fills from high memory to low memory. The address
mode –(SP) creates a new item on the active system stack, and the address mode (SP)
+
deletes an item from the active system stack.
The PC is saved on the active system stack on subroutine calls and is restored from the
active system stack on returns. On the other hand, both the PC and the SR are saved on
the supervisor stack during the processing of traps and interrupts. Thus, the correct
execution of the supervisor state code is not dependent on the behavior of user code, and
user programs may use the USP arbitrarily.