6-4
MC68330 USER’S MANUAL
MOTOROLA
Table 6-2. Boundary Scan Bit Definitions
Bit
Num
Cell
Type
Pin/Cell
Name
Pin
Type
Output
CTL Cell
Bit
Num
Cell
Type
Pin/Cell
Name
Pin
Type
Output
CTL Cell
0
O.Latch
CS3
TS-Output
ab.ctl
54
IO.cell
D11
I/O
db.ctl
1
O.Latch
CS2
TS-Output
ab.ctl
55
IO.cell
D10
I/O
db.ctl
2
O.Latch
CS1
TS-Output
ab.ctl
56
IO.cell
D9
I/O
db.ctl
3
IO.cell
CS0
I/O
cs0.ctl
57
IO.cell
D8
I/O
db.ctl
4
IO.ctl0
cs0.ctl
—
58
IO.cell
A0
I/O*
ab.ctl
5
IO.cell
FC2
I/O*
ab.ctl
59
IO.cell
A31
I/O
a31.ctl
6
IO.cell
FC1
I/O*
ab.ctl
60
IO.ctl0
a31.ctl
—
7
IO.cell
FC0
I/O*
ab.ctl
61
IO.cell
A30
I/O
a30.ctl
8
IO.cell
A1
I/O*
ab.ctl
62
IO.ctl0
a30.ctl
—
9
IO.cell
A2
I/O*
ab.ctl
63
IO.cell
A29
I/O
a29.ctl
10
IO.cell
A3
I/O*
ab.ctl
64
IO.ctl0
a29.ctl
—
11
IO.cell
A4
I/O*
ab.ctl
65
IO.cell
A28
I/O
a28.ctl
12
IO.cell
A5
I/O*
ab.ctl
66
IO.ctl0
a28.ctl
—
13
IO.cell
A6
I/O*
ab.ctl
67
IO.cell
A27
I/O
a27.ctl
14
IO.cell
A7
I/O*
ab.ctl
68
IO.ctl0
a27.ctl
—
15
IO.cell
A8
I/O*
ab.ctl
69
IO.cell
A26
I/O
a26.ctl
16
IO.cell
A9
I/O*
ab.ctl
70
IO.ctl0
a26.ctl
—
17
IO.cell
A10
I/O*
ab.ctl
71
IO.cell
A25
I/O
a25.ctl
18
IO.cell
A11
I/O*
ab.ctl
72
IO.ctl0
a25.ctl
—
19
IO.cell
A12
I/O*
ab.ctl
73
IO.cell
A24
I/O
a24.ctl
20
IO.cell
A13
I/O*
ab.ctl
74
IO.ctl0
a24.ctl
—
21
IO.cell
A14
I/O*
ab.ctl
75
O.Latch
LWE
TS-Output
ab.ctl
22
IO.cell
A15
I/O*
ab.ctl
76
O.Latch
UWE
TS-Output
ab.ctl
23
IO.cell
A16
I/O*
ab.ctl
77
IO.cell
RMC
I/O*
ab.ctl
24
IO.cell
A17
I/O*
ab.ctl
78
IO.ctl1
ab.ctl
—
25
IO.cell
A18
I/O*
ab.ctl
79
IO.ctl0
berr.ctl
—
26
IO.cell
A19
I/O*
ab.ctl
80
IO.ctl1
db.ctl
—
27
IO.cell
A20
I/O*
ab.ctl
81
IO.cell
D7
I/O
db.ctl
28
IO.cell
A21
I/O*
ab.ctl
82
IO.cell
D6
I/O
db.ctl
29
IO.cell
A22
I/O*
ab.ctl
83
IO.cell
D5
I/O
db.ctl
30
IO.cell
A23
I/O*
ab.ctl
84
IO.cell
D4
I/O
db.ctl
31
O.Latch
FREEZE
Output
—
85
IO.cell
D3
I/O
db.ctl
32
I.Pin
BKPT
Input
—
86
IO.cell
D2
I/O
db.ctl
33
IO.cell
IFETCH
I/O*
ifetch.ctl
87
IO.cell
D1
I/O
db.ctl
34
IO.ctl0
ifetch.ctl
—
88
IO.cell
D0
I/O
db.ctl
35
O.Latch
IPIPE
Output
—
89
IO.cell
DSACK0
I/O**
berr.ctl
36
I.Pin
EXTAL
Input
—
90
IO.cell
DSACK1
I/O**
berr.ctl
37
O.Latch
CLKOUT
Output
—
91
I.Pin
BR
Input
—
38
IO.cell
MODCK
I/O
modck.ctl
92
O.Latch
BG
Output
—
39
IO.ctl0
modck.ctl
—
93
I.Pin
BGACK
Input
—
40
O.Latch
RESET
OD-I/O
—
94
IO.cell
IRQ7
I/O
irq7.ctl
41
I.Pin
RESET
OD-I/O
—
95
IO.ctl0
irq7.ctl
—
42
O.Latch
HALT
OD-I/O
—
96
IO.cell
IRQ6
I/O
irq6.ctl
43
I.Pin
HALT
OD-I/O
—
97
IO.ctl0
irq6.ctl
—
44
IO.cell
BERR
I/O**
berr.ctl
98
IO.cell
IRQ5
I/O
irq5.ctl
45
IO.cell
DS
I/O*
ab.ctl
99
IO.ctl0
irq5.ctl
—
46
IO.cell
AS
I/O*
ab.ctl
100
IO.cell
IRQ4
I/O
irq4.ctl
47
IO.cell
R/
W
I/O*
ab.ctl
101
IO.ctl0
irq4.ctl
—
48
IO.cell
SIZ0
I/O*
ab.ctl
102
IO.cell
IRQ3
I/O
irq3.ctl
49
IO.cell
SIZ1
I/O*
ab.ctl
103
IO.ctl0
irq3.ctl
—
50
IO.cell
D15
I/O
db.ctl
104
IO.cell
IRQ2
I/O
irq2.ctl
51
IO.cell
D14
I/O
db.ctl
105
IO.ctl0
irq2.ctl
—
52
IO.cell
D13
I/O
db.ctl
106
IO.cell
IRQ1
I/O
irq1.ctl
53
IO.cell
D12
I/O
db.ctl
107
IO.ctl0
irq1.ctl
—
NOTE: The indicated pins are implemented differently than defined in the signal definition description:
* Input during Motorola factory test
** Output during Motorola factory test