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5- 60
MC68330 USER'S MANUAL
MOTOROLA
All exception vectors, except the reset vector, are located in supervisor data space. The
reset vector is located in supervisor program space. Only the initial reset vector is fixed in
the processor memory map. When initialization is complete, there are no fixed
assignments. Since the VBR stores the vector table base address, the table can be
located anywhere in memory. It can also be dynamically relocated for each task executed
by an operating system.
Each vector is assigned an 8-bit number. Vector numbers for some exceptions are
obtained from an external device; others are supplied by the processor. The processor
multiplies the vector number by four to calculate vector offset, then adds the offset to the
contents of the VBR. The sum is the memory address of the vector.
5.6.1.1 TYPES OF EXCEPTIONS. An exception can be caused by internal or external
events.
An internal exception can be generated by an instruction or by an error. The TRAP,
TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause exceptions
during normal execution. Illegal instructions, instruction fetches from odd addresses, word
or long-word operand accesses from odd addresses, and privilege violations also cause
internal exceptions.
Sources of external exception include interrupts, breakpoints, bus errors, and reset
requests. Interrupts are peripheral device requests for processor action. Breakpoints are
used to support development equipment. Bus error and reset are used for access control
and processor restart.
5.6.1.2 EXCEPTION PROCESSING SEQUENCE. For all exceptions other than a reset
exception, exception processing occurs in the following sequence. Refer to 5.6.2.1 Reset
for details of reset processing.
As exception processing begins, the processor makes an internal copy of the SR. After the
copy is made, the processor state bits in the SR are changed — the S-bit is set,
establishing supervisor access level,and bits T1 and T0 are cleared, disabling tracing. For
reset and interrupt exceptions, the interrupt priority mask is also updated.
Next, the exception number is obtained. For interrupts, the number is fetched from CPU
space $F (the bus cycle is an interrupt acknowledge). For all other exceptions, internal
logic provides a vector number.
Next, current processor status is saved. An exception stack frame is created and placed
on the supervisor stack. All stack frames contain copies of the SR and the PC for use by
RTE. The type of exception and the context in which the exception occurs determine what
other information is stored in the stack frame.
Finally, the processor prepares to resume normal execution of instructions. The exception
vector offset is determined by multiplying the vector number by four, and the offset is
added to the contents of the VBR to determine displacement into the exception vector
table. The exception vector is loaded into the PC. If no other exception is pending, the
processor will resume normal execution at the new address in the PC.
5.6.1.3 EXCEPTION STACK FRAME. During exception processing, the most volatile
portion of the current context is saved on the top of the supervisor stack. This context is
organized in a format called the exception stack frame.