MOTOROLA
MC68330 USER’S MANUAL
3- 17
State 0 – The read cycle starts in state 0 (S0). During S0, the MC68330 places a valid
address on A31-A0 and valid function codes on FC2-FC0. The function codes
select the address space for the cycle. The MC68330 drives R/
W high for a read
cycle. SIZ1 and SIZ0 become valid, indicating the number of bytes requested for
transfer.
State 1 – One-half clock later, in state 1 (S1), the MC68330 asserts
AS indicating a
valid address on the address bus. The MC68330 also asserts
DS during S1. The
selected device uses R/
W, SIZ1 or SIZ0, A0, and DS to place its information on the
data bus. One or both of the bytes (D15-D8, and D7-D0) are selected by SIZ1,
SIZ0, and A0. Concurrently, the selected device asserts
DSACKx.
State 2 – As long as at least one of the
DSACKx signals is recognized on the falling
edge of S2 (meeting the asynchronous input setup time requirement), data is
latched on the falling edge of S4, and the cycle terminates.
State 3 – If
DSACKx is not recognized by the start of state 3 (S3), the MC68330
inserts wait states instead of proceeding to states 4 and 5. To ensure that wait
states are inserted, both
DSACK1 and DSACK0 must remain negated throughout
the asynchronous input setup and hold times around the end of S2. If wait states
are added, the MC68330 continues to sample
DSACKx on the falling edges of the
clock until one is recognized.
State 4 – At the falling edge of state 4 (S4), the MC68330 latches the incoming data
and samples
DSACKx to get the port size.
State 5 – The MC68330 negates
AS and DS during state 5 (S5). It holds the address
valid during S5 to provide address hold time for memory systems. R/
W, SIZ1 and
SIZ0, and FC2-FC0 also remain valid throughout S5. The external device keeps its
data and
DSACKx signals asserted until it detects the negation of AS or DS
(whichever it detects first). The device must remove its data and negate
DSACKx
within approximately one clock period after sensing the negation of
AS or DS.
DSACKx signals that remain asserted beyond this limit may be prematurely
detected for the next bus cycle.
3.3.2 Write Cycle
During a write cycle, the MC68330 transfers data to memory or a peripheral device. Figure
3-8 is a flowchart of a write cycle operation for a word transfer.