MOTOROLA
MC68330 USER'S MANUAL
4-13
Internal
DSACKx Generation for External Accesses with Programmable Wait States
DSACKx can be generated internally with up to three wait states for a particular
device using the DD bits in the address mask register.
Full 32-Bit Address Decode with Address Space Checking
The FC bits in the base address register and FCM bits in the address mask
register are used to select address spaces for which the chip selects will be
asserted.
4.2.4.2 GLOBAL CHIP-SELECT OPERATION. Global chip-select operation allows
address decode for a boot ROM before system initialization occurs.
CS0 is the global
chip-select output, and its operation differs from the other external chip-select outputs
following reset. When the CPU32 begins fetching after reset,
CS0 is asserted for every
address until the V-bit in the module address base register (MBAR) is set.
Global chip select provides a 16-bit port with three wait states, which allows a boot ROM
to be located in any address space and still provide the stack pointer and program
counter values at $00000000 and $00000004, respectively. Global chip select does not
provide write protection and responds to all function codes.
CS0 operates in this manner
until the V-bit is set in the
CS0 base address register. CS0 can be programmed to
continue decode for a range of addresses after the V-bit is set, provided the desired
address range is first loaded into base address register 0. After the V-bit is set for
CS0,
global chip select can only be restarted with a system reset.
A system can use an 8-bit boot ROM if an external 8-bit DSACK is generated which
responds in two wait states or less. See Section 7 Applications for a discussion.
4.2.5 External Bus Interface
This section describes port A and port B functions. Refer to Section 3 Bus Operation
for more information about the external bus interface.
4.2.5.1 PORT A. Port A pins can be independently programmed to be either
addresses A31–A24, discrete I/O pins, or
IACKx pins. The port A pin assignment
registers (PPARA1 and PPARA2) control the function of the port A pins as shown in
Table 4-4. Upon reset, port A is configured as input pins. If the system uses these signals
as addresses, pulldowns should be put on these signals to avoid indeterminate values
until the port A registers can be programmed.
Table 4-4. Port A Pin Assignment Register Function
Pin Function
Signal
PPARA1 BIT = 0
PPARA1 BIT = 1
PPARA1 BIT = 0
PPARA2 BIT = 0
PPARA2 BIT = X
PPARA2 BIT = 1
A31
PORT A7
IACK7
A30
PORT A6
IACK6
A29
PORT A5
IACK5
A28
PORT A4
IACK4
A27
PORT A3
IACK3
A26
PORT A2
IACK2