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5- 114
MC68330 USER'S MANUAL
MOTOROLA
Although the CPU32 has a two-word instruction pipeline, internal delay causes minimum
branch instruction time to be three bus cycles. The negative tail is a reminder that an extra
two clocks are available for prefetching a third word on a fast bus; on a slower bus, there
is no extra time for the third word.
CLOCK
1
2
3
4
5
6789
01
23
4
BUS
CONTROLLER
INSTRUCTION
CONTROLLER
EXECUTION
TIME
MOVEQ
OFFSET
CALC
56
789
BRANCH OFFSE
BRA.W FARAWAY
TAKEN
FETCH MOVE.L
FETCH NEXT
INSTRUCTION
PREFETCH
MOVE
TO D0
MOVE.L D1,D
MOVEQ #7,D1
Figure 5-45. Example 3 — Branch Negative Tail
Example 3 illustrates three different aspects of instruction time calculation:
The branch instruction does not attempt to prefetch beyond the minimum number of
words needed for itself.
The negative tail allows execution to begin sooner than would a three-word pipeline.
There is a one-clock delay due to late arrival of the displacement at the CPU.
Only changes of flow require negative tail calculation, but the concept can be generalized
to any instruction — only two words are required to be in the pipeline, but up to three
words may be present. When there is an opportunity for an extra prefetch, it is made. A
prefetch to replace an instruction can begin ahead of the instruction, resulting in a faster
processor.
5.8.3 INSTRUCTION TIMING TABLES
The following assumptions apply to the times shown in the tables in this section:
— A 16-bit data bus is used for all memory accesses.
— Memory access times are based on two clock bus cycles with no wait states.
— The instruction pipeline is full at the beginning of the instruction and is refilled by the
end of the instruction.
Three values are listed for each instruction and addressing mode:
Head: The number of cycles available at the beginning of an instruction to complete a
previous instruction write or to perform a prefetch.
Tail: The number of cycles an instruction uses to complete a write.
Cycles: Four numbers per entry, three contained in parentheses. The outer number is
the minimum number of cycles required for the instruction to complete.