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MOTOROLA
MC68330 USER'S MANUAL
5- 115
Numbers within the parentheses represent the number of bus accesses
performed by the instruction. The first number is the number of operand read
accesses performed by the instruction. The second number is the number of
instruction fetches performed by the instruction, including all prefetches that
keep the instruction and the instruction pipeline filled. The third number is the
number of write accesses performed by the instruction.
As an example, consider an ADD.L (12, A3, D7.W
4), D2 instruction.
Paragraph 5.8.3.5 Arithmetic/Logic Instructions shows that the instruction has a head =
0, a tail = 0, and cycles = 2 (0/1/0). However, in indexed, address register indirect
addressing mode, additional time is required to fetch the EA. Paragraph 5.8.3.1 Fetch
Effective Address gives addressing mode data. For (d8, An, Xn.Sz Scale), head = 4,
tail = 2, cycles = 8 (2/1/0). Because this example is for a long access and the FEA table
lists data for word accesses, add two clocks to the tail and to the number of cycles ("X"
table notation) to obtain head = 4, tail = 4, cycles = 10 (2/1/0).
Assuming that no trailing write exists from the previous instruction, EA calculation requires
six clocks. Replacement fetch for the EA occurs during these six clocks, leaving a head of
four. If there is no time in the head to perform a prefetch, due to a previous trailing write,
then additional time to do the prefetches must be allotted in the middle of the instruction or
after the tail.
TOTAL NUMBER OF CLOC
NUMBER OF READ CYCL
NUMBER OF INSTRUCTION ACCESS CY
NUMBER OF WRITE CYCL
8 (2 /1 /0)
The total number of bus-activity clocks is as follows:
(2 Reads
× 2 Clocks/Read) + (1 Instruction Access × 2 Clocks/Access) +
(0 Writes
× 2 Clocks/Write) = 6 Clocks of Bus Activity
The number of internal clocks (not overlapped by bus activity) is as follows:
10 Clocks Total
6 Clocks Bus Activity = 4 Internal Clocks
Memory read requires two bus cycles at two clocks each. This read time, implied in the tail
figure for the EA, cannot be overlapped with the instruction because the instruction has a
head of zero. An additional two clocks are required for the ADD instruction itself. The total
is 6
+ 4 + 2 = 12 clocks. If bus cycles take more time (i.e., the memory is off-chip), add an
appropriate number of clocks to each memory access.
The instruction sequence MOVE.L D0, (A0) followed by LSL.L #7, D2 provides an
example of overlapped execution. The MOVE instruction has a head of zero and a tail of
four, because it is a long write. The LSL instruction has a head of four. The trailing write