4-24
MC68330 USER'S MANUAL
MOTOROLA
This bit controls the software watchdog clock source as shown in 4.3.2.5 System
Protection Control Register (SYPCR).
1=Software watchdog clock prescaled by a value of 512
0=Software watchdog clock not prescaled
The SWP reset value is the inverse of the MODCK bit state on the rising edge of reset.
PTP — Periodic Timer Prescaler Control
This bit contains the prescaler control for the periodic timer.
1=Periodic timer clock prescaled by a value of 512
0=Periodic timer clock not prescaled
The PTP reset value is the inverse of the MODCK bit state on the rising edge of reset.
PITR7–PITR0 — Periodic Interrupt Timer Register Bits 7–0
The remaining bits of the PITR contain the count value for the periodic timer. A
zero value turns off the periodic timer.
4.3.2.8 SOFTWARE SERVICE REGISTER (SWSR). The SWSR is the location to
which the software watchdog servicing sequence is written. The software watchdog can
be enabled or disabled by the SWE bit in the SYPCR. SWSR can be written at any time
but returns all zeros when read.
SWSR
$027
76
5
4
3
2
10
00
000
0
SWSR0
SWSR7SWSR6SWSR5
SWSR3SWSR2 SWSR1
SWSR4
RESET
Supervisor Only
4.3.3 Clock Synthesizer Control Register (SYNCR)
The SYNCR can be read or written only in supervisor mode. The reset state of SYNCR
produces an operating frequency of 8.38-MHz, when the PLL is referenced to a 32.768-
kHz reference signal. The system frequency is controlled by the frequency control bits in
the upper byte of the SYNCR as follows:
FSYSTEM = FCRYSTAL (4(Y+1)22W+X)
SYNCR
$004
15
14
13
12
11
10
9
8
7
6
54
32
1
0
1
111
11
0
0U
U
0
00
RESET
STEXT
STSIM
RSTEN
SLOCK
SLIMP
0
RSVD
Y0
Y1
Y2
Y3
Y4
Y5
X
W
U = Unaffected by reset
Supervisor Only
W — Frequency Control Bit
This bit controls the prescaler tap in the synthesizer feedback loop. Setting the bit
increases the VCO speed by a factor of four, requiring a time delay for the VCO to
relock (see equation for determining system frequency).
X — Frequency Control Bit
This bit controls a divide-by-two prescaler, which is not in the synthesizer
feedback loop. Setting the bit doubles the system clock speed without changing
the VCO speed, as specified in the equation for determining system frequency;
therefore, no delay is incurred to relock the VCO.