3- 18
MC68330 USER’S MANUAL
MOTOROLA
1. NEGATE DS, AS, AND UWE
2. REMOVE DATA FROM D15–
BUS MASTER
SLAVE
ADDRESS DEVICE
1. SET R/W TO WRITE
2. DRIVE ADDRESS ON A31–A0
3. DRIVE FUNCTION CODE ON FC2–FC0
4. DRIVE SIZE PINS FOR OPERAND SIZE
5. ASSERT AS AND UWE/LWE
6. PLACE DATA ON D15–D0
7. ASSERT DS
TERMINATE OUTPUT TRANSFE
START NEXT CYCLE
1. DECODE ADDRESS
2. LATCH DATA FROM D15–D0
ACCEPT DATA
3. ASSERT DSACKx SIGN
TERMINATE CYCLE
1. NEGATE DSAC
Figure 3-8. Write Cycle Flowchart
State 0 – The write cycle starts in S0. During S0, the MC68330 places a valid address
on A31-A0 and valid function codes on FC2-FC0. The function codes select the
address space for the cycle. The MC68330 drives R/
W low for a write cycle. SIZ1
and SIZ0 become valid, indicating the number of bytes to be transferred.
State 1 – One-half clock later, in S1, the MC68330 asserts
AS, indicating a valid
address on the address bus. During this state
UWE and/or LWE is asserted
simultaneously with
AS.
State 2 – During S2, the MC68330 places the data to be written onto D15-D0, and
samples
DSACKx at the end of S2.
State 3 – The MC68330 asserts
DS during S3, indicating that data is stable on the
data bus. As long as at least one of the
DSACKx signals is recognized by the end
of S2 (meeting the asynchronous input setup time requirement), the cycle
terminates one clock later. If
DSACKx is not recognized by the start of S3, the
MC68330 inserts wait states instead of proceeding to S4 and S5. To ensure that
wait states are inserted, both
DSACK1 and DSACK0 must remain negated
throughout the asynchronous input setup and hold times around the end of S2. If
wait states are added, the MC68330 continues to sample
DSACKx on the falling
edges of the clock until one is recognized. The selected device uses R/
W, SIZ1,
SIZ0, and A0 to latch data from the appropriate byte(s) of D15-D8, and D7-D0.
SIZ1, SIZ0, and A0 select the bytes of the data bus. If it has not already done so,
the device asserts
DSACKx to signal that it has successfully stored the data.
State 4 – The MC68330 issues no new control signals during S4.
State 5 – The MC68330 negates
AS and DS during S5. It holds the address and data
valid during S5 to provide address hold time for memory systems. R/
W, SIZ1, SIZ0,
and FC2-FC0 also remain valid throughout S5. The external device must keep