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MOTOROLA
MC68330 USER'S MANUAL
5- 13
The SR shown in Figure 5-5 is 16 bits wide. Only 11 bits of the SR are defined, and all
undefined values are reserved by Motorola for future definition. The undefined bits are
read as zeros and should be written as zeros for future compatibility. The lower byte of the
SR is the CCR. Operations to the CCR can be performed at the supervisor or user
privilege level. All operations to the SR and CCR are word-size operations. For all CCR
operations, the upper byte is read as all zeros and is ignored when written, regardless of
privilege level.
The alternate function code registers (SFC and DFC) are 32-bit registers with only bits 2—
0 implemented. These bits contain address space values (FC2 to FC0) for the read or
write operand of the MOVES instruction. The MOVEC instruction is used to transfer values
to and from the alternate function code registers. These are long-word transfers — the
upper 29 bits are read as zeros and are ignored when written.
5.2.3.2 ORGANIZATION IN MEMORY. Memory is organized on a byte-addressable basis.
An address corresponds to a high-order byte. For example, the address (N) of a long-word
data item is the address of the most significant byte of the high-order word. The address of
the most significant byte of the low-order word is (N
+ 2), and the address of the least
significant byte of the long word is (N
+ 3). The CPU32 requires data words and long
words, as well as instruction words, to be aligned on word boundaries. Data misalignment
is not supported. Figure 5-8 shows how operands and instructions are organized in
memory. Note that (N
+ X) is below (N) — that is, address value increases as one moves
down the page.
5.3 DATA ORGANIZATION AND ADDRESSING CAPABILITIES
The addressing mode of an instruction can specify the value of an operand (an immediate
operand), a register that contains the operand (register direct addressing mode), or how
the effective address of an operand in memory is derived. An assembler syntax has been
defined for each addressing mode.
Figure 5-9 shows the general format of the single effective-address-instruction operation
word. The effective address field specifies the addressing mode for an operand that can
use one of the numerous defined modes. The designation is composed of two 3-bit fields,
the mode field and the register field. The value in the mode field selects a mode or a set of
modes. The register field specifies a register for the mode or a submode for modes that do
not use registers.
Many instructions imply the addressing mode for only one of the operands. The formats of
these instructions include appropriate fields for operands that use only a single addressing
mode.