- 您现在的位置：买卖IC网 > PDF目录299522 > MT45W2MW16BBB-856WT 2M X 16 PSEUDO STATIC RAM, 85 ns, PBGA54 PDF资料下载
参数资料
| 型号： | MT45W2MW16BBB-856WT |
| 元件分类： | SRAM |
| 英文描述： | 2M X 16 PSEUDO STATIC RAM, 85 ns, PBGA54 |
| 封装： | 6 X 8 MM, 1 MM HEIGHT, 0.75 MM PITCH, LEAD FREE, VFBGA-54 |
| 文件页数： | 16/56页 |
| 文件大小： | 709K |
| 代理商： | MT45W2MW16BBB-856WT |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页
4 MEG x 16, 2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
09005aef80be1fbd pdf/09005aef80be2036 zip
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_2.fm - Rev. D 9/04 EN
23
2003 Micron Technology, Inc. All rights reserved.
Deep Power-Down (RCR[4])
Default = DPD Disabled
The deep power-down bit enables and disables all
refresh-related activity. This mode is used if the system
does not require the storage provided by the Cellular-
RAM device. Any stored data will become corrupted
when DPD is enabled. When refresh activity has been
re-enabled, the CellularRAM device will require 150s
to perform an initialization procedure before normal
operations can resume.
Deep power-down is enabled when RCR[4] = 0, and
remains enabled until RCR[4] is set to “1.” DPD should
not be enabled or disabled with the software access
sequence; instead, use CRE to access the RCR.
Temperature Compensated Refresh (RCR[6:5])
Default = +85°C Operation
The TCR bits allow for adequate refresh at four dif-
ferent temperature thresholds (+15°C, +45°C, +70°C,
and +85°C). The setting selected must be for a tem-
perature higher than the case temperature of the
CellularRAM device. If the case temperature is
+50°C, the system can minimize self refresh current
consumption by selecting the +70°C setting. The
+15°C and +45°C settings would result in inadequate
refreshing and cause data corruption.
Page Mode Operation (RCR[7])
Default = Disabled
The page mode operation bit determines whether
page mode is enabled for asynchronous READ opera-
tions. In the power-up default state, page mode is dis-
abled.
Table 6:
64Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
ADDRESS SPACE
SIZE
DENSITY
0
Full die
000000h–3FFFFFh
4 Meg x 16
64Mb
0
1
One-half of die
000000h–1FFFFFh
2 Meg x 16
32Mb
0
1
0
One-quarter of die
000000h–0FFFFFh
1 Meg x 16
16Mb
0
1
One-eighth of die
000000h–07FFFFh
512K x 16
8Mb
1
0
None of die
0
0 Meg x 16
0Mb
1
0
1
One-half of die
200000h–3FFFFFh
2 Meg x 16
32Mb
1
0
One-quarter of die
300000h–3FFFFFh
1 Meg x 16
16Mb
1
One-eighth of die
380000h–3FFFFFh
521K x 16
8Mb
Table 7:
32Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
ADDRESS SPACE
SIZE
DENSITY
0
Full die
000000h–1FFFFFh
2 Meg x 16
32Mb
0
1
One-half of die
000000h–0FFFFFh
1 Meg x 16
16Mb
0
1
0
One-quarter of die
000000h–07FFFFh
512K x 16
8Mb
0
1
One-eighth of die
000000h–03FFFFh
256K x 16
4Mb
1
0
None of die
0
0 Meg x 16
0Mb
1
0
1
One-half of die
100000h–1FFFFFh
1 Meg x 16
16Mb
1
0
One-quarter of die
180000h–1FFFFFh
512K x 16
8Mb
1
One-eighth of die
1C0000h–1FFFFFh
256K x 16
4Mb
相关PDF资料 |
PDF描述 |
|---|---|
| MT46H32M32LGCM-5IT:A | 32M X 32 DDR DRAM, 5 ns, PBGA90 |
| MT46HC32M16LFCX-75:B | 32M X 16 DDR DRAM, 7.5 ns, PBGA90 |
| MT46HC32M16LGCM-54IT:B | 32M X 16 DDR DRAM, 5.4 ns, PBGA90 |
| MT47H32M16BT-37VL:A | 32M X 16 DDR DRAM, 0.5 ns, PBGA92 |
| MT47H64M16HQ-3IT:G | 64M X 16 DDR DRAM, 0.4 ns, PBGA60 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT45W2MW16BFB-601 WT | 制造商:Micron Technology Inc 功能描述: |
| MT45W2MW16BFB-701 WT | 制造商:Micron Technology Inc 功能描述: |
| MT45W2MW16BFB-706 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS 54VFBGA - Trays |
| MT45W2MW16BFB-708 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS - Trays |
| MT45W2MW16BFB-856 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 85NS 54VFBGA - Trays |
发布紧急采购，3分钟左右您将得到回复。