参数资料
型号: MT45W2MW16BBB-856WT
元件分类: SRAM
英文描述: 2M X 16 PSEUDO STATIC RAM, 85 ns, PBGA54
封装: 6 X 8 MM, 1 MM HEIGHT, 0.75 MM PITCH, LEAD FREE, VFBGA-54
文件页数: 25/56页
文件大小: 709K
代理商: MT45W2MW16BBB-856WT
4 MEG x 16, 2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
09005aef80be1fbd pdf/09005aef80be2036 zip
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_2.fm - Rev. D 9/04 EN
31
2003 Micron Technology, Inc. All rights reserved.
NOTE:
1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh
opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than
15ns.
2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
Table 17:
Burst WRITE Cycle Timing Requirements
PARAMETER
SYMBOL
-701
-708
-706/-856
UNITS
NOTES
MIN
MAX
MIN
MAX
MIN
MAX
CE# HIGH between Subsequent
Mixed-Mode Operations
tCBPH
55
5
ns
1
Minimum CE# Pulse Width
tCEM
88
8
s
1
CE# LOW to WAIT Valid
tCEW
17.517.517.5
ns
Clock Period
tCLK
9.62
20
12.5
20
15
20
ns
2
CE# Setup to CLK Active Edge
tCSP
4
20
4.5
20
5
20
ns
Hold Time from Active CLK Edge
tHD
22
2
ns
Chip Disable to WAIT High-Z Output
tHZ
88
8
ns
CLK Rise or Fall Time
tKHKL
1.6
1.8
2.0
ns
Clock to WAIT Valid
tKHTL
79
11
ns
CLK HIGH or LOW Time
tKP
34
5
ns
Setup Time to Activate CLK Edge
tSP
3
ns
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相关代理商/技术参数
参数描述
MT45W2MW16BFB-601 WT 制造商:Micron Technology Inc 功能描述:
MT45W2MW16BFB-701 WT 制造商:Micron Technology Inc 功能描述:
MT45W2MW16BFB-706 WT 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS 54VFBGA - Trays
MT45W2MW16BFB-708 WT 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS - Trays
MT45W2MW16BFB-856 WT 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 85NS 54VFBGA - Trays