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参数资料
| 型号： | MT45W2MW16BBB-856WT |
| 元件分类： | SRAM |
| 英文描述： | 2M X 16 PSEUDO STATIC RAM, 85 ns, PBGA54 |
| 封装： | 6 X 8 MM, 1 MM HEIGHT, 0.75 MM PITCH, LEAD FREE, VFBGA-54 |
| 文件页数： | 51/56页 |
| 文件大小： | 709K |
| 代理商： | MT45W2MW16BBB-856WT |
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4 MEG x 16, 2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
09005aef80be1fbd pdf/09005aef80be2036 zip
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_2.fm - Rev. D 9/04 EN
55
2003 Micron Technology, Inc. All rights reserved.
Revision History
Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/04
WE# LOW limited to tCEM for async WRITES.
Last address changed by software access sequence.
Noted software access third cycle must be CE#-
controlled WRITE.
Separated ICC3 for READ and WRITE.
Moved tCPH to follow CE#-controlled async WRITE
cycles only.
CRE is “Don’t Care” during burst continue.
Clarified TCR temperatures and setting in Table 9.
Changed VccQ to 1.7V–3.3V.
Changed wireless temperature range to -30°C.
Noted input HIGH voltage not aligned with the
workgroup specification of VCCQ - 0.4.
Noted wireless temp exceeds the workgroup spec.
Clarified WAIT assertion for continuous burst with
output delay.
Noted workgroup spec for burst termination
compliance.
Rev. C, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/04
Added software access.
CR WRITE diagram titles updated to reflect WRITEs
followed by READ ARRAY operation.
Added 80 MHz burst clock (-708).
Changed PAR options to full, one-half, one-quarter,
one-eight, or none.
Corrected Table 16 typo.
Clarified READ/WRITE operating currents.
Added clarifying notes for required refresh
opportunity for BCR[15], depending on BCR setting.
Changed tCEM MAX to 8.
Updated ICC values and symbols.
and Table 46.
Clarified CE# LOW time limited by refresh—must
not stay LOW longer than tCEM.
Aligned tACLK, tKHTL, tABA, and tCSP with
consortium values.
Added tCEM to Asynchronous WRITE, Page Mode
READ Operation, and Burst Mode Operation
descriptions and timing diagrams.
Deleted Appendix A (extended timings and all
references).
Added -708 timing specifications.
Added CIN and CIO MIN values.
Clarified burst latency at row-boundary crossings.
Replaced Abbreviated Component Marks with Part
Numbering chart.
Added measurement time clarification to ISB and
IPAR notes.
Changed tCBPH to tCPH for async–async
transitions.
Corrected package nomenclature to VFBGA.
Clarified address A[4] and higher in page mode.
Clarified CRE in Figure 14.
Updated tKP to 4ns for the -708, and 5ns for -706
and -856 parts.
Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/03
Changed BCR[6] = 0 to “not supported,” and deleted
all references to falling clock edges.
Clarified mixed-mode operation.
104MHz part now “contact factory.”
Changed tHD MIN in all speed grades to 2.
Prohibited DPD via software access sequence.
Changed tCSP (MIN) to 5ns for -706 and -856 in all
burst timing tables (18, 20, 25, 26, 27, 28, 34, 36, 37,
39, 41).
Added “and ADV# LOW” to tAS in Async WRITE
Timing Req. table; added tAS as appropriate in
Figures 34, 38, 41, 43, and corollary Tables 38, 44, 48.
Added Note 6 to Tables 2 and 3 for Standby Mode,
and clarified standby description under Low-Power
Operation.
-701 latency code 2 (3 clocks) changed to 66 MHz
(15.2ns).
Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/03
Added lead-free option.
Differentiated standard and low-power standby and
related annotation in/for figures and tables.
CLK in Tables 2 & 3 changed; can be either HIGH or
LOW. Data and figures added to cover software
access to the configuration registers.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT45W2MW16BFB-601 WT | 制造商:Micron Technology Inc 功能描述: |
| MT45W2MW16BFB-701 WT | 制造商:Micron Technology Inc 功能描述: |
| MT45W2MW16BFB-706 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS 54VFBGA - Trays |
| MT45W2MW16BFB-708 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS - Trays |
| MT45W2MW16BFB-856 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 85NS 54VFBGA - Trays |
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