参数资料
型号: MT45W2MW16BBB-856WT
元件分类: SRAM
英文描述: 2M X 16 PSEUDO STATIC RAM, 85 ns, PBGA54
封装: 6 X 8 MM, 1 MM HEIGHT, 0.75 MM PITCH, LEAD FREE, VFBGA-54
文件页数: 21/56页
文件大小: 709K
代理商: MT45W2MW16BBB-856WT
4 MEG x 16, 2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
09005aef80be1fbd pdf/09005aef80be2036 zip
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_2.fm - Rev. D 9/04 EN
28
2003 Micron Technology, Inc. All rights reserved.
NOTE:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. Page-mode enabled only.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 23 on page 27. The Low-Z timings measure a 100mV
transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
4. Low-Z to High-Z timings are tested with the circuit shown in Figure 23 on page 27. The High-Z timings measure a 100mV
transition from either VOH or VOL toward VCCQ/2.
Table 14:
Asynchronous READ Cycle Timing Requirements
PARAMETER1
SYMBOL
-70x
-856
UNITS NOTES
MIN
MAX
MIN
MAX
Address Access Time
tAA
70
85
ns
ADV# Access Time
tAADV
70
85
ns
Page Access Time
tAPA
20
25
ns
Address Hold from ADV# HIGH
tAVH
55
ns
Address Setup to ADV# HIGH
tAVS
10
ns
LB#/UB# Access Time
tBA
70
85
ns
LB#/UB# Disable to DQ High-Z Output
tBHZ
88
ns
4
LB#/UB# Enable to Low-Z Output
tBLZ
10
ns
3
Maximum CE# Pulse Width
tCEM
88
s
2
CE# LOW to WAIT Valid
tCEW
17.517.5
ns
Chip Select Access Time
tCO
70
85
ns
CE# LOW to ADV# HIGH
tCVS
10
ns
Chip Disable to DQ and WAIT High-Z Output
tHZ
88
ns
4
Chip Enable to Low-Z Output
tLZ
10
ns
3
Output Enable to Valid Output
tOE
20
ns
Output Hold from Address Change
tOH
55
ns
Output Disable to DQ High-Z Output
tOHZ
88
ns
4
Output Enable to Low-Z Output
tOLZ
55
ns
3
Page Cycle Time
tPC
20
25
ns
READ Cycle Time
tRC
70
85
ns
ADV# Pulse Width LOW
tVP
10
ns
ADV# Pulse Width HIGH
tVPH
10
ns
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