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参数资料
| 型号： | MT45W2MW16BBB-856WT |
| 元件分类： | SRAM |
| 英文描述： | 2M X 16 PSEUDO STATIC RAM, 85 ns, PBGA54 |
| 封装： | 6 X 8 MM, 1 MM HEIGHT, 0.75 MM PITCH, LEAD FREE, VFBGA-54 |
| 文件页数： | 53/56页 |
| 文件大小： | 709K |
| 代理商： | MT45W2MW16BBB-856WT |
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4 MEG x 16, 2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
09005aef80be1fbd pdf/09005aef80be2036 zip
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_2.fm - Rev. D 9/04 EN
6
2003 Micron Technology, Inc. All rights reserved.
l
NOTE:
The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. WAIT will
be asserted but should be ignored during asynchronous and page mode operations.
Table 1:
VFBGA Ball Descriptions
VFBGA
ASSIGNMENT
SYMBOL
TYPE
DESCRIPTION
A3, A4, A5, B3,
B4, C3, C4, D4,
H2, H3, H4, H5,
G3, G4, F3, F4,
E4, D3, H1, G2,
H6, E3
A[21:0]
Input
Address Inputs: Inputs for addresses during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address lines
are also used to define the value to be loaded into the BCR or the RCR. On the
32Mb device, A21 (ball E3) is not internally connected.
J2
CLK
Input
Clock: Synchronizes the memory to the system operating frequency during
synchronous operations. When configured for synchronous operation, the address
is latched on the first rising CLK edge when ADV# is active. CLK is static (HIGH or
LOW) during asynchronous access READ and WRITE operations and during PAGE
READ ACCESS operations.
J3
ADV#
Input
Address Valid: Indicates that a valid address is present on the address inputs.
Addresses can be latched on the rising edge of ADV# during asynchronous READ
and WRITE operations. ADV# may be held LOW during asynchronous READ and
WRITE operations.
A6
CRE
Input
Control Register Enable: When CRE is HIGH, WRITE operations load the RCR or
BCR.
B5
CE#
Input
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby or deep power-down mode.
A2
OE#
Input
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
G5
WE#
Input
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle
is a WRITE to either a configuration register or to the memory array.
A1
LB#
Input
Lower Byte Enable. DQ[7:0]
B2
UB#
Input
Upper Byte Enable. DQ[15:8]
B6, C5, C6, D5,
E5, F5, F6, G6,
B1, C1, C2, D2,
E2, F2, F1, G1
DQ[15:0]
Input/
Output
Data Inputs/Outputs.
J1
WAIT
Output
Wait: Provides data-valid feedback during burst READ and WRITE operations. The
signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and
READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary.
WAIT is also used to mask the delay associated with opening a new internal page.
WAIT is asserted and should be ignored during asynchronous and page mode
operations. WAIT is High-Z when CE# is HIGH.
J4, J5, J6
NC
–
Not internally connected.
D6
VCC
Supply
Device Power Supply: (1.70V–1.95V) Power supply for device core operation.
E1
VCCQ
Supply
I/O Power Supply: (1.70V–3.30V) Power supply for input/output buffers.
E6
VSS
Supply
VSS must be connected to ground.
D1
VSSQ
Supply
VSSQ must be connected to ground.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT45W2MW16BFB-601 WT | 制造商:Micron Technology Inc 功能描述: |
| MT45W2MW16BFB-701 WT | 制造商:Micron Technology Inc 功能描述: |
| MT45W2MW16BFB-706 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS 54VFBGA - Trays |
| MT45W2MW16BFB-708 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS - Trays |
| MT45W2MW16BFB-856 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 85NS 54VFBGA - Trays |
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