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参数资料
| 型号： | MT45W2MW16BBB-856WT |
| 元件分类： | SRAM |
| 英文描述： | 2M X 16 PSEUDO STATIC RAM, 85 ns, PBGA54 |
| 封装： | 6 X 8 MM, 1 MM HEIGHT, 0.75 MM PITCH, LEAD FREE, VFBGA-54 |
| 文件页数： | 6/56页 |
| 文件大小： | 709K |
| 代理商： | MT45W2MW16BBB-856WT |
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4 MEG x 16, 2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
09005aef80be1fbd pdf/09005aef80be2036 zip
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_2.fm - Rev. D 9/04 EN
14
2003 Micron Technology, Inc. All rights reserved.
Low-Power Operation
Standby Mode Operation
During standby, the device current consumption is
reduced to the level necessary to perform the DRAM
refresh operation. Standby operation occurs when CE#
is HIGH.
The device will enter a reduced power state upon
completion of a READ or WRITE operation, or when
the address and control inputs remain static for an
extended period of time. This mode will continue until
a change occurs to the address or control inputs.
Temperature Compensated Refresh
Temperature compensated refresh (TCR) is used to
adjust the refresh rate depending on the device oper-
ating
temperature.
DRAM
technology
requires
increasingly frequent refresh operations to maintain
data integrity as temperatures increase. More frequent
refresh is required due to increased leakage of the
DRAM capacitive storage elements as temperatures
rise. A decreased refresh rate at lower temperatures
will facilitate a savings in standby current.
TCR allows for adequate refresh at four different
temperature thresholds (+15°C, +45°C, +70°C, and
+85°C). The setting selected must be for a temperature
higher than the case temperature of the CellularRAM
device. For example, if the case temperature is +50°C,
the system can minimize self refresh current con-
sumption by selecting the +70°C setting. The +15°C
and +45°C settings would result in inadequate refresh-
ing and cause data corruption.
Partial Array Refresh
Partial array refresh (PAR) restricts refresh opera-
tion to a portion of the total memory array. This fea-
ture enables the device to reduce standby current by
refreshing only that part of the memory array required
by the host system. The refresh options are full array,
one-half array, one-quarter array, one-eighth array, or
none of the array. The mapping of these partitions can
start at either the beginning or the end of the address
READ and WRITE operations to address ranges receiv-
ing refresh will not be affected. Data stored in
addresses not receiving refresh will become corrupted.
When re-enabling additional portions of the array, the
new portions are available immediately upon writing
to the RCR.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all
refresh-related activity. This mode is used if the system
does not require the storage provided by the Cellular-
RAM device. Any stored data will become corrupted
when DPD is enabled. When refresh activity has been
re-enabled by rewriting the RCR, the CellularRAM
device will require 150s to perform an initialization
procedure before normal operations can resume. Dur-
ing this 150s period, the current consumption will be
higher than the specified standby levels, but consider-
ably lower than the active current specification.
DPD cannot be enabled or disabled by writing to
the RCR using the software access sequence; the RCR
should be accessed using CRE instead.
Configuration Registers
Two user-accessible configuration registers define
the device operation. The bus configuration register
(BCR) defines how the CellularRAM interacts with the
system memory bus and is nearly identical to its coun-
terpart on burst mode Flash devices. The refresh config-
uration register (RCR) is used to control how refresh is
performed on the DRAM array. These registers are
automatically loaded with default settings during
power-up, and can be updated any time the devices
are operating in a standby state.
Access Using CRE
The configuration registers are loaded using either a
synchronous or an asynchronous WRITE operation
when the control register enable (CRE) input is HIGH
a READ or WRITE operation will access the memory
array. The register values are placed on addresses
A[21:0]. In an asynchronous WRITE, the values are
latched into the configuration register on the rising
edge of ADV#, CE#, or WE#, whichever occurs first; LB#
and UB# are “Don’t Care.” Access using CRE is WRITE
only. The BCR is accessed when A[19] is HIGH; the
RCR is accessed when A[19] is LOW.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT45W2MW16BFB-601 WT | 制造商:Micron Technology Inc 功能描述: |
| MT45W2MW16BFB-701 WT | 制造商:Micron Technology Inc 功能描述: |
| MT45W2MW16BFB-706 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS 54VFBGA - Trays |
| MT45W2MW16BFB-708 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS - Trays |
| MT45W2MW16BFB-856 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 85NS 54VFBGA - Trays |
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