参数资料
型号: MT45W2MW16BBB-856WT
元件分类: SRAM
英文描述: 2M X 16 PSEUDO STATIC RAM, 85 ns, PBGA54
封装: 6 X 8 MM, 1 MM HEIGHT, 0.75 MM PITCH, LEAD FREE, VFBGA-54
文件页数: 8/56页
文件大小: 709K
代理商: MT45W2MW16BBB-856WT
4 MEG x 16, 2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
09005aef80be1fbd pdf/09005aef80be2036 zip
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_2.fm - Rev. D 9/04 EN
16
2003 Micron Technology, Inc. All rights reserved.
Figure 13: Configuration Register WRITE in Synchronous Mode
Followed by READ ARRAY Operation
NOTE:
1. Non-default BCR settings for configuration register WRITE in synchronous mode followed by READ ARRAY operation:
Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused by
refresh collisions require a corresponding number of additional CE# LOW cycles.
CLK
A[21:0]
(except A19)
A192
CRE
ADV#
CE#
OE#
WE#
LB#/UB#
WAIT
DQ[15:0]
tSP
tHD
tCSP
tSP
tHD
High-Z
DON’T CARE
OPCODE
ADDRESS
High-Z
tCW
Latch Control Register Value
Latch Control Register Address
tCBPH3
DATA
VALID
ADDRESS
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