参数资料
型号: MT45W2MW16BBB-856WT
元件分类: SRAM
英文描述: 2M X 16 PSEUDO STATIC RAM, 85 ns, PBGA54
封装: 6 X 8 MM, 1 MM HEIGHT, 0.75 MM PITCH, LEAD FREE, VFBGA-54
文件页数: 24/56页
文件大小: 709K
代理商: MT45W2MW16BBB-856WT
4 MEG x 16, 2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
09005aef80be1fbd pdf/09005aef80be2036 zip
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_2.fm - Rev. D 9/04 EN
30
2003 Micron Technology, Inc. All rights reserved.
NOTE:
1. High-Z to Low-Z timings are tested with the circuit shown in Figure 23 on page 27. The Low-Z timings measure a 100mV
transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 23 on page 27. The High-Z timings measure a 100mV
transition from either VOH or VOL toward VCCQ/2.
3. WE# LOW time must be limited to tCEM (8s).
Table 16:
Asynchronous WRITE Cycle Timing Requirements
PARAMETER
SYMBOL
-70x
-856
UNITS
NOTES
MIN
MAX
MIN
MAX
Address and ADV# LOW Setup Time
tAS
00
ns
Address Hold from ADV# Going HIGH
tAVH
55
ns
Address Setup to ADV# Going HIGH
tAVS
10
ns
Address Valid to End of WRITE
tAW
70
85
ns
LB#/UB# Select to End of WRITE
tBW
70
85
ns
CE# LOW to WAIT Valid
tCEW
17.517.5
ns
Async Address-to-Burst Transition Time
tCKA
70
85
ns
CE# HIGH between Subsequent Asynchronous Operations tCPH
55
ns
CE# LOW to ADV# HIGH
tCVS
10
ns
Chip Enable to End of WRITE
tCW
70
85
ns
Data Hold from WRITE Time
tDH
00
ns
Data WRITE Setup Time
tDW
23
ns
Chip Disable to WAIT High-Z Output
tHZ
88
ns
Chip Enable to Low-Z Output
tLZ
10
ns
1
End WRITE to Low-Z Output
tOW
55
ns
1
ADV# Pulse Width
tVP
10
ns
ADV# Pulse Width HIGH
tVPH
10
ns
ADV# Setup to End of WRITE
tVS
70
85
ns
WRITE Cycle Time
tWC
70
85
ns
WRITE to DQ High-Z Output
tWHZ
88
ns
2
WRITE Pulse Width
tWP
46
55
ns
3
WRITE Pulse Width HIGH
tWPH
10
ns
WRITE Recovery Time
tWR
00
ns
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