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参数资料
| 型号： | MT45W2MW16BBB-856WT |
| 元件分类： | SRAM |
| 英文描述： | 2M X 16 PSEUDO STATIC RAM, 85 ns, PBGA54 |
| 封装： | 6 X 8 MM, 1 MM HEIGHT, 0.75 MM PITCH, LEAD FREE, VFBGA-54 |
| 文件页数： | 45/56页 |
| 文件大小： | 709K |
| 代理商： | MT45W2MW16BBB-856WT |
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4 MEG x 16, 2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
09005aef80be1fbd pdf/09005aef80be2036 zip
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_2.fm - Rev. D 9/04 EN
5
2003 Micron Technology, Inc. All rights reserved.
General Description
Micron CellularRAM products are high-speed,
CMOS dynamic random access memories developed
for
low-power,
portable
applications.
The
MT45W4MW16BFB is a 64Mb device organized as 4
Meg x 16 bits; the MT45W2MW16BFB is a 32Mb
device organized as 2 Meg x 16 bits. These devices
include an industry-standard burst mode Flash
interface that dramatically increases read/write band-
width compared with other low-power SRAM or
Pseudo SRAM offerings.
To operate seamlessly on a burst Flash bus, Cellu-
larRAM products incorporate a transparent self refresh
mechanism. The hidden refresh requires no additional
support from the system memory controller and has
no significant impact on device read/write perfor-
mance.
Two user-accessible control registers define device
operation. The bus configuration register (BCR)
defines how the CellularRAM device interacts with the
system memory bus and is nearly identical to its coun-
terpart on burst mode Flash devices. The refresh con-
figuration register (RCR) is used to control how refresh
is performed on the DRAM array. These registers are
automatically loaded with default settings during
power-up and can be updated anytime during normal
operation.
Special attention has been focused on standby cur-
rent consumption during self refresh. CellularRAM
products include three system-accessible mechanisms
used to minimize standby current. Partial array refresh
(PAR) limits refresh to only that part of the DRAM array
that contains essential data. Temperature compen-
sated refresh (TCR) is used to adjust the refresh rate
according to the case temperature. The refresh rate
can be decreased at lower temperatures to minimize
current consumption during standby. Deep power-
down (DPD) halts the refresh operation altogether and
is used when no vital information is stored in the
device. These three refresh mechanisms are accessed
through the RCR.
Figure 1: Functional Block Diagram—4 Meg x 16 and 2 Meg x 16
NOTE:
Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing
diagrams for detailed information.
A[21:0]
(for 64Mb)
A[20:0]
(for 32Mb)
Input/
Output
MUX
and
Buffers
Control
Logic
4,096K x 16
(2,048K x 16)
DRAM
MEMORY
ARRAY
CE#
WE#
OE#
CLK
ADV#
CRE
WAIT
LB#
UB#
DQ[7:0]
DQ[15:8]
Address Decode
Logic
Refresh Configuration
Register (RCR)
Bus Configuration
Register (BCR)
相关PDF资料 |
PDF描述 |
|---|---|
| MT46H32M32LGCM-5IT:A | 32M X 32 DDR DRAM, 5 ns, PBGA90 |
| MT46HC32M16LFCX-75:B | 32M X 16 DDR DRAM, 7.5 ns, PBGA90 |
| MT46HC32M16LGCM-54IT:B | 32M X 16 DDR DRAM, 5.4 ns, PBGA90 |
| MT47H32M16BT-37VL:A | 32M X 16 DDR DRAM, 0.5 ns, PBGA92 |
| MT47H64M16HQ-3IT:G | 64M X 16 DDR DRAM, 0.4 ns, PBGA60 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT45W2MW16BFB-601 WT | 制造商:Micron Technology Inc 功能描述: |
| MT45W2MW16BFB-701 WT | 制造商:Micron Technology Inc 功能描述: |
| MT45W2MW16BFB-706 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS 54VFBGA - Trays |
| MT45W2MW16BFB-708 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS - Trays |
| MT45W2MW16BFB-856 WT | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 85NS 54VFBGA - Trays |
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