R8C/38T-A Group
13. DTC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 164 of 730
Aug 05, 2011
13. DTC
The DTC (data transfer controller) is a function that transfers data between the SFR and on-chip memory without using
the CPU. The DTC is activated by a peripheral function interrupt to perform data transfers. The DTC and CPU use the
same bus, and the DTC takes priority over the CPU in using the bus.
To control DTC data transfers, control data comprised of a transfer source address, a transfer destination address, and
operating modes are allocated in the DTC control data area. Each time the DTC is activated, the DTC reads control
data to perform data transfers.
13.1
Overview
i = 0 to 3, 5, or 6, j = 0 to 23
Table 13.1
DTC Specifications
Item
Specification
Activation sources
27 sources
Allocatable control data
24 sets
Address space which can be
transferred
64 Kbytes (00000h to 0FFFFh)
Maximum
number of
transfers
Normal mode
256 times
Repeat mode
255 times
Maximum size
of block to be
transferred
Normal mode
256 bytes
Repeat mode
255 bytes
Unit of transfers
Byte
Transfer mode
Normal mode
Transfers end on completion of the transfer causing the DTCCTj register value to
change from 1 to 0.
Repeat mode
On completion of the transfer causing the DTCCTj register value to change from
1 to 0, the repeat area address is initialized and the DTRLDj register value is
reloaded to the DTCCTj register to continue transfers.
Address control
Normal mode
Fixed or incremented
Repeat mode
Addresses of the area not selected as the repeat area are fixed or incremented.
Priority of activation sources
Refer to Table 13.8 DTC Activation Sources and DTC Vector Addresses.
Interrupt
request
Normal mode
When the data transfer causing the DTCCTj register value to change from 1 to 0
is performed, the activation source interrupt request is generated for the CPU,
and interrupt handling is performed on completion of the data transfer.
Repeat mode
When the data transfer causing the DTCCTj register value to change from 1 to 0
is performed while the RPTINT bit in the DTCCRj register is 1 (interrupt
generation enabled), the activation source interrupt request is generated for the
CPU, and interrupt handling is performed on completion of the transfer.
Transfer start
When bits DTCENi0 to DTCENi7 in the DTCENi registers are set to 1 (activation
enabled), data transfer is started each time the corresponding DTC activation
sources are generated.
Transfer stop
Normal mode
When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled).
When the data transfer causing the DTCCTj register value to change from 1 to
0 is completed.
Repeat mode
When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled).
When the data transfer causing the DTCCTj register value to change from 1 to
0 is completed while the RPTINT bit is 1 (interrupt generation enabled).