R8C/38T-A Group
17. Timer RC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 286 of 730
Aug 05, 2011
17.2.4
Timer RC Control Register 1 (TRCCR1)
Notes:
1. The values set by bits TOA to TOD are reflected immediately after they are changed. Set the value when the
CTS bit in the TRCMR register is 0 (count stops).
2. When selecting fHOCO, set these bits with the on-chip oscillator operating. When switching the count sources,
set these bits with the counter stopped.
This bit is used to set the output value from the TRCIOA pin until the first compare match A (match between
the values of registers TRCCNT and TRCGRA) occurs. In PWM mode, this bit is used to control the output
level of the TRCIOA pin.
This bit is used to set the output value from the TRCIOB pin until the first compare match B (match between
the values of registers TRCCNT and TRCGRB) occurs. In PWM mode and PWM2 mode, this bit is used to
control the output level of the TRCIOB pin.
This bit is used to set the output value from the TRCIOC pin until the first compare match C (match between
the values of registers TRCCNT and TRCGRC) occurs. In PWM mode, this bit is used to control the output
level of the TRCIOC pin.
This bit is used to set the output value from the TRCIOD pin until the first compare match D (match between
the values of registers TRCCNT and TRCGRD) occurs. In PWM mode, this bit is used to control the output
level of the TRCIOD pin.
Address 00143h (TRCCR1_0)
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
000
0000
Bit
Symbol
Bit Name
Function
R/W
b0
TOA
Timer output level select A bit
0: Output value is low
(1)1: Output value is high
(1)R/W
b1
TOB
Timer output level select B bit
R/W
b2
TOC
Timer output level select C bit
R/W
b3
TOD
Timer output level select D bit
R/W
b4
CKS0
Count source select bits
b6 b5 b4
0 0 0: f1
0 0 1: f2
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: Rising edge of TRCCLK input
1 1 1: fHOCO-F
R/W
b5
CKS1
R/W
b6
CKS2
R/W
b7
CCLR
TRCCNT counter clear select bit
0: Free-running counter
1: TRCCNT counter is cleared by input
capture/compare match A
R/W