R8C/38T-A Group
17. Timer RC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 288 of 730
Aug 05, 2011
17.2.6
Timer RC Status Register (TRCSR)
Notes:
1. The edge is selected by bits IOi0 to IOi1 (i = A to D) in registers TRCIO0 and TRCIOR1. However, all of bits
IOA2 and IOB2 in the TRCIOR0 register and bits IOC2 and IOD2 in the TRCIOR1 register must be set to 1
(input capture function).
2. PWM mode is selected when bits PWMB, PWMC, and PWMD in the TRCMR register are set to 1.
Address 00145h (TRCSR_0)
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
111
0000
Bit
Symbol
Bit Name
Function
R/W
b0
IMFA
Input capture/compare match A flag
[Conditions for setting to 0]
When 0 is written to this bit after reading it as 1.
Set to 0 by the DTC acknowledge when the DTC
is activated by an IMFi interrupt (i = A to D).
[Condition for setting to 1]
.
R/W
b1
IMFB
Input capture/compare match B flag
R/W
b2
IMFC
Input capture/compare match C flag
R/W
b3
IMFD
Input capture/compare match D flag
R/W
b4
—
Nothing is assigned. The write value must be 1. The read value is 1.
—
b5
—
b6
—
b7
OVF
Timer overflow flag
[Condition for setting to 0]
When 0 is written to this bit after reading it as 1.
[Condition for setting to 1]
.
R/W
Table 17.5
Conditions for Setting Each Flag to 1
Symbol
Timer Mode
PWM Mode
PWM2 Mode
Input Capture Function
Output Compare
Function
IMFA
When the value of the TRCCNT register
is transferred to the TRCGRA register
at the input edge
(1) of the TRCIOA pin.
When the values of registers TRCCNT and TRCGRA match
IMFB
When the value of the TRCCNT register
is transferred to the TRCGRB register
at the input edge
(1) of the TRCIOB pin.
When the values of registers TRCCNT and TRCGRB match
(compare match B).
IMFC
When the value of the TRCCNT register
is transferred to the TRCGRC register
at the input edge
(1) of the TRCIOC pin.
When the values of registers TRCCNT and TRCGRC match
(compare match C).
IMFD
When the value of the TRCCNT register
is transferred to the TRCGRD register
at the input edge
(1) of the TRCIOD pin.
When the values of registers TRCCNT and TRCGRD match
(compare match D).
OVF
When the TRCCNT register overflows from FFFFh to 0000h.