R8C/38T-A Group
13. DTC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 174 of 730
Aug 05, 2011
Figure 13.2
Block Diagram Showing Control of DTC Activation Sources (i = 0 to 3, 5, or 6)
13.3.3
Control Data Allocation and DTC Vector Table
Control data is allocated in the order: Registers DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj
j = 0 to 23
Table 13.7
Control Data Allocation Addresses
Control Data
No.
Address
DTCCRj
Register
DTBLSj
Register
DTCCTj
Register
DTRLDj
Register
DTSARj
Register
(Lower
8 Bits)
DTSARj
Register
(Higher
8 Bits)
DTDARj
Register
(Lower
8 Bits)
DTDARj
Register
(Higher
8 Bits)
Control data 0
06C40h to 06C47h
06C40h
06C41h
06C42h
06C43h
06C44h
06C45h
06C46h
06C47h
Control data 1
06C48h to 06C4Fh
06C48h
06C49h
06C4Ah
06C4Bh
06C4Ch
06C4Dh
06C4Eh
06C4Fh
Control data 2
06C50h to 06C57h
06C50h
06C51h
06C52h
06C53h
06C54h
06C55h
06C56h
06C57h
Control data 3
06C58h to 06C5Fh
06C58h
06C59h
06C5Ah
06C5Bh
06C5Ch
06C5Dh
06C5Eh
06C5Fh
Control data 4
06C60h to 06C67h
06C60h
06C61h
06C62h
06C63h
06C64h
06C65h
06C66h
06C67h
Control data 5
06C68h to 06C6Fh
06C68h
06C69h
06C6Ah
06C6Bh
06C6Ch
06C6Dh
06C6Eh
06C6Fh
Control data 6
06C70h to 06C77h
06C70h
06C71h
06C72h
06C73h
06C74h
06C75h
06C76h
06C77h
Control data 7
06C78h to 06C7Fh
06C78h
06C79h
06C7Ah
06C7Bh
06C7Ch
06C7Dh
06C7Eh
06C7Fh
Control data 8
06C80h to 06C87h
06C80h
06C81h
06C82h
06C83h
06C84h
06C85h
06C86h
06C87h
Control data 9
06C88h to 06C8Fh
06C88h
06C89h
06C8Ah
06C8Bh
06C8Ch
06C8Dh
06C8Eh
06C8Fh
Control data 10
06C90h to 06C97h
06C90h
06C91h
06C92h
06C93h
06C94h
06C95h
06C96h
06C97h
Control data 11
06C98h to 06C9Fh
06C98h
06C99h
06C9Ah
06C9Bh
06C9Ch
06C9Dh
06C9Eh
06C9Fh
Control data 12
06CA0h to 06CA7h
06CA0h
06CA1h
06CA2h
06CA3h
06CA4h
06CA5h
06CA6h
06CA7h
Control data 13
06CA8h to 06CAFh
06CA8h
06CA9h
06CAAh
06CABh
06CACh
06CADh
06CAEh
06CAFh
Control data 14
06CB0h to 06CB7h
06CB0h
06CB1h
06CB2h
06CB3h
06CB4h
06CB5h
06CB6h
06CB7h
Control data 15
06CB8h to 06CBFh
06CB8h
06CB9h
06CBAh
06CBBh
06CBCh
06CBDh
06CBEh
06CBFh
Control data 16 06CC0h to 06CC7h
06CC0h
06CC1h
06CC2h
06CC3h
06CC4h
06CC5h
06CC6h
06CC7h
Control data 17 06CC8h to 06CCFh
06CC8h
06CC9h
06CCAh
06CCBh
06CCCh
06CCDh
06CCEh
06CCFh
Control data 18 06CD0h to 06CD7h
06CD0h
06CD1h
06CD2h
06CD3h
06CD4h
06CD5h
06CD6h
06CD7h
Control data 19 06CD8h to 06CDFh
06CD8h
06CD9h
06CDAh
06CDBh
06CDCh
06CDDh
06CDEh
06CDFh
Control data 20
06CE0h to 06CE7h
06CE0h
06CE1h
06CE2h
06CE3h
06CE4h
06CE5h
06CE6h
06CE7h
Control data 21
06CE8h to 06CEFh
06CE8h
06CE9h
06CEAh
06CEBh
06CECh
06CEDh
06CEEh
06CEFh
Control data 22
06CF0h to 06CF7h
06CF0h
06CF1h
06CF2h
06CF3h
06CF4h
06CF5h
06CF6h
06CF7h
Control data 23
06CF8h to 06CFFh
06CF8h
06CF9h
06CFAh
06CFBh
06CFCh
06CFDh
06CFEh
06CFFh
Interrupt controller
Select interrupt source or
DTC activation source
DTCENi
Clear control
Peripheral function 1
(SSU/I
2C) (1)
Peripheral function 2
(Other than SSU/I
2C)
DTC
Interrupt request
Peripheral interrupt
request
Peripheral interrupt
request
DTC activation
request
Select DTC activation or
interrupt generation.
Set the bit among bits DTCENi0 to
DTCENi7 to 0.
Set the interrupt source flag
in the status register to 0.
Note:
1. For the clock synchronous serial interface (SSU/I
2C), the interrupt source flag is cleared by DTC data transfer.