R8C/38T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 470 of 730
Aug 05, 2011
21.2.7.2
I2C bus Function
Notes:
1. When writing to bits BC0 to BC2, write 0 to the BC3 bit simultaneously using the MOV instruction. The write value
of bits BC0 to BC2 when 1 is written is invalid.
2. After data including the acknowledge bit is transferred, bits BC2 to BC0 are automatically set to 000b. When a
start condition is detected, these bits are automatically set to 000b.
3. Do not rewrite this bit in clock synchronous serial mode.
4. The setting value is valid in master mode of I2C bus interface mode. The value is invalid in slave mode of I2C bus
interface mode and in clock synchronous serial mode.
5. Set to 0 in I2C bus interface mode.
Address 000E8h (SIMR1_0)
Bit
b7
b6
b5
b4b3b2
b1b0
Symbol
After Reset
0
011
000
Bit
Symbol
Bit Name
Function
R/W
b0
BC0
Bit counters 0 to 2
I2C bus interface mode (Read: Number of
remaining transfer bits; Write: Number of next
b2 b1 b0
0 0 1: 2 bits
0 1 0: 3 bits
0 1 1: 4 bits
1 0 0: 5 bits
1 0 1: 6 bits
1 1 0: 7 bits
1 1 1: 8 bits
Clock synchronous serial mode (Read: Number
of remaining transfer bits; Write: Always 000b)
b2 b1 b0
0 0 0: 8 bits
0 0 1: 1 bit
0 1 0: 2 bits
0 1 1: 3 bits
1 0 0: 4 bits
1 0 1: 5 bits
1 1 0: 6 bits
1 1 1: 7 bits
R/W
b1
BC1
R/W
b2
BC2
R/W
b3
BC3
Bit counter 3
When rewriting bits BC0 to BC2, write 0 to this
bit simultaneously.
(1, 3) The read value is 1.
R/W
b4
—
Nothing is assigned. The write value must be 1. The read value is 1.
—
b5
CPHS
Reserved
Set to 0.
R/W
b6
CPOS_WAIT Wait insertion bit
(4)0: No wait states (Data and the acknowledge bit
are transferred consecutively)
1: Wait states (After the clock of the last data bit
falls, a low-level period is extended for two
transfer clocks)
R/W
b7
MLS
MSB first/LSB first select bit
0: Data transfer with MSB first
(5)1: Data transfer with LSB first
R/W