R8C/38T-A Group
7. Voltage Detection Circuit
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 67 of 730
Aug 05, 2011
7.2.7
Voltage Monitor 2 Circuit Control Register (VW2C)
Notes:
1. The VW2C0 bit is enabled when the VCA27 bit in the VCA2 register is 1 (voltage detection 2 circuit enabled).
When the VCA27 bit is 0 (voltage detection 2 circuit disabled), set the VW2C0 bit to 0 (disabled). To set the
2. When the digital filter is used (the VW2C1 bit is 0), set the CM14 bit in the CM1 register to 0 (low-speed on-chip
oscillator on).
When the voltage monitor 2 interrupt is used to exit stop mode, set the VW2C1 bit to 1 (digital filter disabled
mode).
3. When the VW2C0 bit is 1 (enabled), do not set bits VW2C1 and VW2F0 to VW2F1 at the same time (with one
instruction).
4. Bits VW2C2 and VW2C3 are enabled when the VC27 bit is 1 (voltage detection 2 circuit enabled).
5. Set to 0 by a program. This bit is set to 0 by writing 0 by a program, but writing 1 has no effect.
6. The VW2C7 bit is enabled when the VCAC2 bit in the VCAC register is 0 (one edge). Set the VCAC2 bit to 0
before setting the VW2C7 bit.
Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW2C register. Rewriting the
VW2C register may set the VW2C2 bit to 1. Rewrite this register before setting the VW2C2 bit to 0.
Address 0003Ah
Bit
b7b6
b5b4b3
b2b1b0
Symbol
VW2C7
—
VW2F1
VW2F0
VW2C3
VW2C2
VW2C1
VW2C0
After Reset
1
000
1010
Bit
Symbol
Bit Name
Function
R/W
b0
VW2C0
Voltage monitor 2 interrupt enable bit
(1)0: Disabled
1: Enabled
R/W
b1
VW2C1
Voltage monitor 2 digital filter mode
0: Digital filter enabled mode
(digital filter circuit enabled)
1: Digital filter disabled mode
(digital filter circuit disabled)
R/W
b2
VW2C2
Voltage change detection flag
(4, 5)0: Not detected
1: Detected by passing through Vdet2
R/W
b3
VW2C3
Voltage detection 2 signal monitor flag
0: VCC
Vdet2
1: VCC
Vdet2 or voltage detection 2 circuit
disabled
R
b4
VW2F0
Sampling clock select bits
(3)b5 b4
0 0: fLOCO divided by 1
0 1: fLOCO divided by 2
1 0: fLOCO divided by 4
1 1: fLOCO divided by 8
R/W
b5
VW2F1
R/W
b6
—
Reserved
Set to 0.
R/W
b7
VW2C7
Voltage monitor 2 interrupt generation
0: VCC reaches Vdet2 or above
1: VCC reaches Vdet2 or below
R/W