R8C/38T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 515 of 730
Aug 05, 2011
Figure 21.32
Register Setting Example in Master Receive Mode (I2C bus Interface Mode)
End
RDRF = 1?
Master receive mode
No
Yes
(1) Set the TEND bit to 0 and set to master receive mode.
Set the TDRE bit to 0.
(1, 2)
(2) Set the CEIE_ACKBT bit to the transmit device.
(1)
(3) Dummy read the SIRDR register.
(1)
(4) Wait until 1 byte is received.
(5) Determine (last receive - 1).
(6) Read the receive data.
(7) Set the ACKBT bit of the last byte and set continuous
receive operation to disable (RCVD = 1).
(2)
(8) Read the receive data of (last byte - 1).
(9) Wait until the last byte is received.
(10) Set the STOP bit to 0.
(11) Generate a stop condition.
(12) Wait until a stop condition is generated.
(13) Read the receive data of the last byte.
(14) Set the RCVD bit to 0.
(15) Set to slave receive mode.
SICR1 register
TRS bit
0
Dummy read SIRDR register
Read RDRF bit in SISR register
Last receive - 1?
SISR register
TEND bit
0
SISR register
STOP bit
0
SICR2 register
SCP bit
0
BBSY bit
0
Read STOP bit in SISR register
STOP = 1?
SISR register
TDRE bit
0
No
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(12)
(10)
(13)
(14)
(11)
(9)
(15)
SIER register
CEIE_ACKBT bit
0
No
Yes
Read SIRDR register
SIER register
CEIE_ACKBT bit
1
SICR1 register
RCVD bit
1
Read SIRDR register
Read RDRF bit in SISR register
RDRF = 1?
Read SIRDR register
SICR1 register
RCVD bit
0
SICR1 register
MST bit
0
No
Yes
Notes:
1. Do not generate interrupts during process steps (1) to (3).
2. For 1 byte of data reception, skip steps (2) to (6) after step (1) and jump to process step (7). Process step (8) is a dummy
read from the SIRDR register.