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R8C/38T-A Group
18. Timer RE2
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 345 of 730
Aug 05, 2011
18.2.14 Timer RE2 Clock Error Correction Register (TREADJ)
The TREADJ register is used in real-time clock mode. This register is used to set the clock error correction
direction and the correction amount. Write to the TREADJ register while the CS3 bit in the TRECSR register is
1. Change the TREADJ register when the BSY bit in the TRESEC register and the TADJSF bit in the TREIFR
register are both 0.
The one-second counter is changed depending on the values of bits ADJ0 to ADJ5.
When the PLUS bit is set to 0 and the MINUS bit is set to 1, the internal counter is corrected to the minus side.
The clock can be set backward when it gains time.
When the PLUS bit is set to 1 and the MINUS bit is set to 0, the internal counter is corrected to the plus side.
The clock can be set forward when it loses time.
The interval for correction differs depending on the AADJE bit in the TRECR register.
When the AADJE bit is 0 (automatic correction function disabled (correction by software enabled)), correction
is performed when writing to the TREADJ register. When the AADJE bit is 1 (automatic correction function
enabled (correction by software disabled)), correction is performed for the interval set by the AADJM bit in the
TRECSR register.
Address 00179h
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
000
0000
After reset by
RTCRST bit in
TRECR register
0
000
0000
Bit
Symbol
Bit Name
Function
R/W
b0
ADJ0
Correction value setting bits
Setting range: 00h to 3Fh (00 to 63)
R/W
b1
ADJ1
R/W
b2
ADJ2
R/W
b3
ADJ3
R/W
b4
ADJ4
R/W
b5
ADJ5
R/W
b6
MINUS
Correction counter bits
b7 b6
0 0: Not corrected
0 1: Subtraction correction
1 0: Addition correction
1 1: Do not set.
R/W
b7
PLUS
R/W