R8C/38T-A Group
11. Interrupts
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 154 of 730
Aug 05, 2011
11.7
Address Match Interrupt
An address match interrupt request is generated immediately before execution of the instruction at the address
indicated by the AIADRij register (i = 0 or 1, j = L or H). This interrupt is used as a break function for the debugger.
When the on-chip debugger is used, do not set an address match interrupt (registers AIENi, AIADRij, and fixed
vector table) in the user system.
Set the start address of any instruction in the AIADRij register. The AIENi0 bit in the AIENi register can be used to
enable or disable the interrupt. The address match interrupt is not affected by the I flag in the FLG register and IPL.
request is acknowledged, will differ depending on the instruction at the address indicated by the AIADRij register.
(The appropriate return address is not saved on the stack.) Therefore, when returning from the address match
interrupt, use one of the following methods:
Rewrite the contents of the stack and use the REIT instruction to return.
Use an instruction such as POP to restore the stack to its previous state where the interrupt request was
acknowledged. Then use a jump instruction to return.
Notes:
2. Operation code: Refer to the R8C/5x Series User’s manual: Software (R01US0007EJ).
Chapter 4. Instruction Code/Number of Cycles
contains diagrams showing operation code
below each syntax. Operation code is shown in the bold frame in the diagrams.
Table 11.11
PC Value Saved when Address Match Interrupt Request is Acknowledged
Instruction at Address Indicated by AIADRij Register (i = 0 or 1, j = L or H)
Instruction with 2-byte operation code
(2) Instruction with 1-byte operation code
(2)ADD.B:S
#IMM8, dest
SUB.B:S
#IMM8, dest
AND.B:S
#IMM8,dest
OR.B:S
#IMM8, dest
MOV.B:S
#IMM8, dest
STZ
#IMM8,dest
STNZ
#IMM8, dest
STZX
#IMM81, #IMM82,dest
CMP.B:S
#IMM8, dest
PUSHM
src
POPM
dest
JMPS
#IMM8
JSRS
#IMM8
MOV.B:S
#IMM, dest (however, dest = A0 or A1)
Address indicated by
AIADRij register + 2
Instructions other than above
Address indicated by
AIADRij register + 1
Table 11.12
Correspondence between Address Match Interrupt Sources and Associated
Registers
Address Match Interrupt Source
Address Match Interrupt Enable Bit
Address Match Interrupt Register
Address match interrupt 0
AIEN00
AIADR0j
Address match interrupt 1
AIEN10
AIADR1j