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R8C/38T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 485 of 730
Aug 05, 2011
Figure 21.10
Sample Flowchart for Data Reception (MST = 1) (Clock Synchronous Communication
Mode)
Start
Initialization
Dummy read SIRDR register
Read receive data in SIRDR register
Last data
received?
Read RDRF bit in SISR register
RDRF = 1 ?
No
Yes
(1)
(2)
(5)
(1) After setting each register for the synchronous serial
communication unit, the receive operation is started
by performing a dummy read of the SIRDR register.
(3) Confirm that the RDRF bit is 1. If the RDRF bit is
set to 1, read the receive data in the SIRDR
register. When the SIRDR register is read, the
RDRF bit is automatically set to 0.
ORER = 1 ?
End
Read receive data in SIRDR register
Read ORER bit in SISR register
RDRF = 1 ?
SIER register
RE bit
0
SICR1 register
RCVD bit
1
SICR1 register
RCVD bit
0
(7) Confirm that the RDRF bit is 1. To complete the
receive operation, set the RCVD bit to 0 and the RE
bit to 0 before reading the last 1 byte of data.
If the SIRDR register is read without setting the RE
bit to 0, the receive operation is restarted again.
(4) Determine whether the currently outputting clock is
the last 1 byte of data to be received.
If so, set the clock to stop after the data is
received.
Read ORER bit in SISR register
ORER = 1 ?
Read RDRF bit in SISR register
No
(3)
(4)
(6)
(7)
No
Yes
Overrun
error
processing
Yes
No
Yes
No
Yes
(2), (6) If a receive error occurs, perform error
processing after reading the ORER bit. Then
set the ORER bit to 0. Transmission/reception
cannot be restarted while the ORER bit is 1.
(5) While receiving the last 1 byte of data, set the
RCVD bit in the SICR1 register to 1 before reading
the [last frame - 1] of the data and then stop the
clock after the data is received.