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R8C/38T-A Group
10. Power Control
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 126 of 730
Aug 05, 2011
Figure 10.5
Procedure for Reducing Internal Power Consumption Using SVC0 Bit
SVC0
0 (transition to low-power-consumption
mode disabled)
(2)
(The above isautomatically set
when exiting wait mode)
Exit from wait mode
by an interrupt
(Note 1)
Interrupt handling completed
If the high-speed
clock or high-speed
on-chip oscillator
starts in the
interrupt routine,
execute steps (1) to
(3) at the end of the
routine.
Start the XIN clock or
high-speed on-chip oscillator clock
Enter high-speed clock mode or
high-speed on-chip oscillator mode
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Stop the XIN clock and
high-speed on-chip oscillator clock
SVC0
1
(transition to low-power-consumption mode
enabled)
(2, 3)
(Wait until the XIN clock or high-speed on-chip
oscillator clock oscillation stabilizes)
Interrupt handling
In the interrupt routine
If it is necessary to
start the high-speed
clock or high-speed
on-chip oscillator in
the interrupt
routine, execute
steps (6) and (7) in
the routine.
Step (5)
Step (6)
Step (7)
Step (8)
Step (1)
Step (2)
Step (3)
Procedure for reducing internal power
consumption enabled by SVC0
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Stop the XIN clock and
high-speed on-chip oscillator clock
SVC0
1
(transition to low-power-consumption mode
enabled)
(2, 3)
Enter wait mode
(4)
Step (1)
SVC0
0
(transition to low-power-consumption mode
disabled)
(2)
Start the XIN clock or
high-speed on-chip oscillator clock
(Wait until the XIN clock or high-speed on-chip
oscillator clock oscillation stabilizes)
Enter high-speed clock mode or
high-speed on-chip oscillator mode
Step (2)
Step (3)
Step (4)
Step (5)
Step (6)
Step (7)
Step (8)
SVC0: Bit in SVDC register
Notes:
1. Execute this routine for all interrupt processing that occurs in wait mode .
However, this is not required if it is not necessary to start the high-speed clock or high-speed on-chip oscillator in the interrupt routine.
2. Do not write 0 to the SVC0 bit with the instruction immediately after 1 is written to the SVC0 bit. Sequential writes in the opposite order are
also not allowed.
3. When the SVC0 bit is 1, do not set the CM10 bit in the CM1 register to 1 (stop mode).
4. For entering wait mode, refer to the Wait Mode section in the Notes on Power Control section.