R8C/38T-A Group
10. Power Control
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 121 of 730
Aug 05, 2011
To use a peripheral function interrupt to exit wait mode, the following items must be set before executing the
WAIT instruction:
(1) Set the interrupt priority level in bits ILVL0 to ILVL2 in the interrupt priority level registers for the
peripheral function interrupts that are used to exit wait mode. Also, set 000b (interrupt disabled) in bits
ILVL2 to ILVL0 for the peripheral function interrupts that are not to be used to exit wait mode.
(2) Operate the peripheral functions to be used to exit wait mode.
(3) Set the I flag in the FLG register to 1.
When a peripheral function interrupt is used for exiting, the time (number of cycles) from interrupt request
generation to the next instruction execution is as shown in
Figure 10.3, depending on the settings of the FMSTP
bit in the FMR0 register and the SVC0 bit in the SVDC register.
The CPU clock when a peripheral function interrupt is used to exit wait mode is the clock set by bits CM35,
CM36, and CM37 in the CM3 register. At this time, the CM06 bit in the CM0 register and bits CM16 and
CM17 in the CM1 register are automatically changed.
Figure 10.3
Time from Wait Mode after WAIT Instruction Execution to Interrupt Routine Execution
0
(transition to low-power
consumption mode disabled)
1
(transition to low-power
consumption mode enabled)
0
(transition to low-power
consumption mode disabled)
1
(transition to low-power
consumption mode enabled)
Wait mode
Interrupt request generated
Flash memory
activation sequence
T1
CPU clock
restart sequence
T2
Internal power
stabilization time
T0
100
s (max.)
Time until
CPU Clock
Supply (T2)
Remarks
FMSTP Bit
FMR0 Register
Internal Power
Stabilization
Time (T0)
The total on the
left amounts to
the time from
wait mode to
interrupt routine
execution.
SVC0 Bit
SVDC Register
Time until
Flash Memory
Activation (T1)
0
(flash
memory
operates)
1
(flash
memory
stops)
0
s
100
s (max.)
0
s
100
s (max.)
Period of system clock
1 cycle + 60 s (max.)
Period of system clock
1 cycle
Period of CPU clock
2 cycles
Same as above
Time for
Interrupt
Sequence (T3)
Period of CPU clock
20 cycles
Same as above
Interrupt sequence
T3