R8C/38T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 480 of 730
Aug 05, 2011
Note that bits TDRE and TEND in the SISR register are automatically set to 0 by writing transmit data to the
SITDR register and the RDRF bit in the SISR register is automatically set to 0 by reading the SIRDR register. In
particular, the TDRE bit is set back to 1 (data is transferred from registers SITDR to SISDR) at the same time
transmit data is written to the SITDR register. If the TDRE bit is set to 0 (data is not transferred from registers
SITDR to SISDR) by any method other than the above (register access by software), an additional 1 byte of
transferred data may be transmitted.
21.3.1.5
Communication Modes and Pin Functions
The synchronous serial communication unit changes the functions of the I/O pins in each communication mode
according to the settings of the MST bit in the SICR1 register and bits RE_STIE and TE_NAKIE in the SIER
—: Used as a programmable I/O port.
MS, BIDE: Bits in SIMR2 register
MST: Bit in SICR1 register
TE_NAKIE, RE_STIE: Bits in SIER register
Note:
1. Do not set both the TE_NAKIE and RE_STIE bits to 1 in 4-wire bus (bidirectional) communication mode.
Table 21.8
Association between Communication Modes and I/O Pins
Communication
Mode
Bit Setting
Pin State
MS
BIDE
MST
TE_NAKIE
RE_STIE
SSI
SSO
SSCK
Clock synchronous
communication
mode
0
Disabled
0
1
Input
—
Input
1
0
—
Output
Input
1
Input
Output
Input
1
0
1
Input
—
Output
1
0
—
Output
1
Input
Output
4-wire bus
communication
mode
10
00
1
—
Input
1
0
Output
—
Input
1
Output
Input
1
0
1
Input
—
Output
1
0
—
Output
1
Input
Output
4-wire bus
(bidirectional)
communication
11
00
1
—
Input
1
0
—
Output
Input
1
0
1
—
Input
Output
1
0
—
Output