R8C/38T-A Group
23. A/D Converter
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 553 of 730
Aug 05, 2011
23.3.3.2
Trigger from Timer RC
This trigger is selected when bits ADCAP1 and ADCAP0 in the ADMOD register are set to 10b (timer RC).
To use this function, the following conditions must be met:
Bits ADCAP1 and ADCAP0 in the ADMOD register are set to 10b (timer RC).
Timer RC is used in the output compare function (timer mode, PWM mode, PWM2 mode).
The ADTRGjE bit (j = A, B, C, D) in the TRCADCR register is set to 1 (A/D trigger occurs at compare match
with TRCGRj register).
The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts).
When the IMFj bit in the TRCSR register is changed from 0 to 1, A/D conversion starts.
timer RC and the output compare function (timer mode, PWM mode, and PWM2 mode).
23.3.3.3
Event Input Trigger from Event Link Controller (ELC)
When bits ADCAP1 and ADCAP0 in the ADMOD register are set to 11b (event input trigger from ELC), A/D
conversion can be started by event input from the ELC.
An example using INT0 as the A/D conversion start trigger is described below:
Set bits ADCAP1 and ADCAP0 in the ADMOD register to 11b.
Set the INT0EN bit in the INTEN register to 1 (INT0 input enabled), the INT0PL bit to 0 (one edge), and the
INT0POL bit in the INTPOL register to 0 (falling edge selected).
Set the PD4_5 bit in the PD4 register to 0 (input mode).
Select the INT0 digital filter using bits INT0F0 and INT0F1 in the INTF register.
Set bits ELSEL3 to ELSEL0 in the ELSELR0 register to 0001b (A/D converter selected as link destination
peripheral module)
Set the ADST bit in the ADCON0 register to 1 (A/D conversion starts).
When the input to the INT0 pin changes from high to low, A/D conversion starts.
23.3.3.4
Re-Inputting Triggers
Allow one or more conversion cycles (when fAD =
AD, minimum 43 cycles) between A/D conversion start
trigger inputs.