R8C/38T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 466 of 730
Aug 05, 2011
21.2.5.2
I2C bus Function
Notes:
1. In master mode, set these bits according to the required transfer rate. For details on the transfer rate, refer to
and 21.10 Transfer Rate Examples. In slave mode, a transfer clock is used for maintaining the data
.
2. Rewrite the TRS bit between transfer frames.
3. In slave receive mode, when the first 7 bits after the start condition match the slave address set in the SIMR2
register and the 8th bit is 1, the TRS bit is set to 1 (transmit mode).
4. If arbitration is lost in master mode of I2C bus interface mode, bits MST and TRS are set to 0 and slave receive
mode is entered.
5. In multimaster operation, use the MOV instruction to set bits TRS and MST.
6. When the TRS bit is 1, do not set the RCVD bit to 1.
7. When an overrun error occurs in master receive mode of clock synchronous serial mode, the MST bit is set to 0
and slave receive mode is entered.
8. When the MST bit is 0 (slave mode), do not set the RCVD bit to 1.
9. When 0 is written to the ICE bit or 1 is written to the SIRST bit in the SICR2 register while the I2C bus function is
operating, the values of the BBSY bit in the SICR2 register and the STOP bit in the SISR register may be
Address 000E6h (SICR1_0)
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
000
0000
Bit
Symbol
Bit Name
Function
R/W
b0
CKS0
Transfer clock select bits
(1)b3 b2 b1 b0
0 0 0 0: f1/28
0 0 0 1: f1/40
0 0 1 0: f1/48
0 0 1 1: f1/64
0 1 0 0: f1/80
0 1 0 1: f1/100
0 1 1 0: f1/112
0 1 1 1: f1/128
1 0 0 0: f1/56
1 0 0 1: f1/80
1 0 1 0: f1/96
1 0 1 1: f1/128
1 1 0 0: f1/160
1 1 0 1: f1/200
1 1 1 0: f1/224
1 1 1 1: f1/256
R/W
b1
CKS1
R/W
b2
CKS2
R/W
b3
CKS3
R/W
b4
TRS
Transmit/receive select bit
0: Receive mode
1: Transmit mode
R/W
b5
MST
0: Slave mode
1: Master mode
R/W
b6
RCVD
After the SIRDR register is read while TRS = 0,
0: Next receive operation continues
1: Next receive operation disabled
R/W
b7
ICE
I2C bus interface enable bit (9) 0: Output from SCL and SDA is disabled
(Input to SCL and SDA is enabled)
1: Transfer with I2C bus function is enabled
R/W