R8C/38T-A Group
20. Serial Interface (UART2)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 432 of 730
Aug 05, 2011
Notes:
1. If one of the bits listed below is changed, the interrupt source, the interrupt timing, and so on, change.
Bits SMD0 to SMD2 in the U2MR register, the IICM bit in the U2SMR register, the IICM2 bit in the U2SMR2
register, and the CKPH bit in the U2SMR3 register.
2. Second data transfer to the U2RB register (rising edge of SCL2 9th bit)
3. First data transfer to the U2RB register (falling edge of SCL2 9th bit)
Table 20.11
I2C Mode Functions
Function
IICM2 = 0 (NACK/ACK interrupt)
IICM2 = 1
(UART transmit/receive interrupt)
CKPH = 0
(No clock delay)
CKPH = 1
(With clock delay)
CKPH = 0
(No clock delay)
CKPH = 1
(With clock delay)
UART2 bus collision
Start condition detection or stop condition detection
UART2 transmit/NACK2
No acknowledgment detection (NACK)
Rising edge of SCL2 9th bit
UART2
transmission
Rising edge of SCL2
9th bit
UART2
transmission
Falling edge of
SCL2 next to 9th bit
UART2 receive/ACK2
Acknowledgment detection (ACK)
Rising edge of SCL2 9th bit
UART2 reception
Falling edge of SCL2 9th bit
Timing for transferring data
from UART receive shift
register to U2RB register
Acknowledgment detection (ACK)
Rising edge of SCL2 9th bit
Falling edge of
SCL2 9th bit
Falling and rising
edges of SCL2 9th
bit
UART2 transmission output
delay
Delay can be set
Noise filter width
100 ns
Initial value of SCL2
High
Low
High
Low
Acknowledgment detection (ACK)
UART2 reception
Falling edge of SCL2 9th bit
UART2
transmission
Rising edge of SCL2
9th bit
UART2
transmission
Falling edge of
SCL2 next to 9th bit
UART2
transmission
Rising edge of SCL2
9th bit
UART2
transmission
Falling edge of
SCL2 next to 9th bit
Storage of receive data
1st to 8th bits are stored in bits b0 to b7 in
the U2RB register.
1st to 7th bits of the received data are
stored in bits b0 to b6 in the U2RB register.
8th bit is stored in bit b8 in the U2RB
register.
1st to 8th bits are
stored in bits b0 to
b7 in the U2RB
Read of receive data
The U2RB register state is read without modification.
Bits b0 to b6 in the
U2RB register are
read as bits b1 to 7.
Bit b8 in the U2RB
register is read as