R8C/38T-A Group
17. Timer RC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 290 of 730
Aug 05, 2011
17.2.8
Timer RC I/O Control Register 1 (TRCIOR1)
Notes:
1. In buffer operation, registers TRCGRA and TRCGRC, and registers TRCGRB and TRCGRD are paired. The
same values must be set in the IOC2 bit and the IOA2 bit in the TRCIOR0 register, and in the IOD2 bit and the
IOB2 bit in the TRCIOR0 register, respectively.
2. When the input capture function is used, do not rewrite the TRCIOR1 register while the timer is counting.
The setting of the TRCIOR1 register is invalid in PWM mode and PWM2 mode.
Address 00147h (TRCIOR1_0)
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
1
000
1000
Bit
Symbol
Bit Name
Function
R/W
b0
IOC0
TRCGRC control
C0 bit
[IOC3 = 0 (general register for TRCIOA pin)]
b1 b0
0 0: Pin output by compare match C is disabled
0 1: Low output from TRCIOA pin at compare match C
1 0: High output from TRCIOA pin at compare match C
1 1: Toggle output from TRCIOA pin at compare match C
[IOC2 = 0, IOC3 = 1 (output compare register)]
b1 b0
0 0: Pin output by compare match C is disabled
0 1: Low output from TRCIOC pin at compare match C
1 0: High output from TRCIOC pin at compare match C
1 1: Toggle output from TRCIOC pin at compare match C
[IOC2 = 1, IOC3 = 1 (input capture register)]
b1 b0
0 0: Rising edge of TRCIOC pin
0 1: Falling edge of TRCIOC pin
Other than the above: Both edges of TRCIOC pin
R/W
b1
IOC1
TRCGRC control
C1 bit
R/W
b2
IOC2
TRCGRC control
0: Output compare function
1: Input capture function
R/W
b3
IOC3
TRCGRC control
C3 bit
0: Used as a general register for TRCIOA pin
1: Used as a general register for TRCIOC pin
R/W
b4
IOD0
TRCGRD control
D0 bit
[IOD3 = 0 (general register for TRCIOB pin)]
b5 b4
0 0: Pin output by compare match D is disabled
0 1: Low output from TRCIOB pin at compare match D
1 0: High output from TRCIOB pin at compare match D
1 1: Toggle output from TRCIOB pin at compare match D
[IOD2 = 0, IOD3 = 1 ((output compare register)]
b5 b4
0 0: Pin output by compare match D is disabled
0 1: Low output from TRCIOD pin at compare match D
1 0: High output from TRCIOD pin at compare match D
1 1: Toggle output from TRCIOD pin at compare match D
[IOD2 = 1, IOD3 = 1 (input capture register)]
b5 b4
0 0: Rising edge of TRCIOD pin
0 1: Falling edge of TRCIOD pin
Other than the above: Both edges of TRCIOD pin
R/W
b5
IOD1
TRCGRD control
D1 bit
R/W
b6
IOD2
TRCGRD control
0: Output compare function
1: Input capture function
R/W
b7
IOD3
TRCGRD control
D3 bit
0: Used as a general register for TRCIOB pin
1: Used as a general register for TRCIOD pin
R/W