R8C/38T-A Group
20. Serial Interface (UART2)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 400 of 730
Aug 05, 2011
Notes:
1. When an external clock is selected, the requirements must be met in either of the following states:
- The external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data is output at
the falling edge and receive data is input at the rising edge of the transfer clock)
- The external clock is held low when the CKPOL bit is set to 1 (transmit data is output at the rising edge and
receive data is input at the falling edge of the transfer clock)
2. If an overrun error occurs, the receive data in the U2RB register will not be updated (the previous data will be
read).
Table 20.1
UART2 Specifications (1)
Item
Specification
Clock
synchronous
serial I/O
mode
Pins used
TXD2: Transmit data (output)
RXD2: Receive data (input)
CLK2: Transfer clock (master: output, slave: input)
CTS2: Transmit request signal (input)
RTS2: Receive request signal (output)
Noise filter
10 ns noise filter for CLK2 and RXD2 input
Transfer data format
Transfer data length: 8 bits
Transfer clock
The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(2(n + 1))
fj = f1, f8, f32, or fC1
n = Value set in the U2BRG register (00h to FFh)
The CKDIR bit is set to 1 (external clock): Input from the CLK2 pin
Transmit/receive
control
CTS function, RTS function, or CTS/RTS function disabled selectable
Transmission start
conditions
To start transmission, the following requirements must be met: (1)
The TE bit in the U2C1 register is set to 1 (transmission enabled).
The TI bit in the U2C1 register is set to 0 (data present in the U2TB
register).
If the CTS function is selected, input to the CTS2 pin is low.
Reception start
conditions
To start reception, the following requirements must be met: (1)
The RE bit in the U2C1 register is set to 1 (reception enabled).
The TE bit in the U2C1 register is set to 1 (transmission enabled).
The TI bit in the U2C1 register is set to 0 (data present in the U2TB
register).
If the CTS function is selected, input to the CTS2 pin is low.
Interrupt request
generation timing
For transmission, one of the following conditions can be selected.
-The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty):
When data is transferred from the U2TB register to the UART2 transmit
register (at start of transmission).
-The U2IRS bit is set to 1 (transmission completed):
When data transmission from the UART2 transmit register is completed.
For reception
When data is transferred from the UART2 receive register to the U2RB
register (at completion of reception).
Error detection
Overrun error (2)
This error occurs if the serial interface starts receiving the next unit of data
before reading the U2RB register and receives the 7th bit of the next unit
of data.
Selectable functions
CLK polarity selection
Transfer data I/O can be selected to occur synchronously with the rising or
falling edge of the transfer clock.
LSB first/MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
Continuous receive mode selection
A function that enables reception immediately upon reading the U2RB
register can be selected.
Serial data logic switching
This function inverts the logic value of the transmit/receive data.