R8C/38T-A Group
18. Timer RE2
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 346 of 730
Aug 05, 2011
18.2.15 Timer RE2 Interrupt Flag Register (TREIFR) in Real-Time Clock Mode
[Conditions for setting to 0]
When 0 is written to this bit after reading it. If the result of reading this bit is 1, writing 0 to this bit will set it
to 0.
When an interrupt from the DTC is automatically cleared.
[Condition for setting to 1]
The contents of the timer RE2 alarm register (1) and the timer RE2 data register (2) match (refer to 18.3.5 If the result of reading this bit is 0, writing 0 to this bit will not change its value. If this bit changes from 0 to 1
after the read, the bit will remain 1 even if 0 is written. Writing 1 has no effect.
To confirm the match, set an enable bit in the timer RE2 alarm registers
(1) to 1.
Notes:
1. Timer RE2 alarm registers: TREAMN, TREAHR, and TREAWK
2. Timer RE2 data registers: TREMIN, TREHR, and TREWK
Address 0017Ah
Bit
b7b6
b5b4b3
b2b1b0
After Reset
0
000
0000
After reset by
RTCRST bit in
TRECR register
0
000
0000
Bit
Symbol
Bit Name
Function
R/W
b0
ALIF
Alarm interrupt flag
0: No interrupt requested
1: Interrupt requested
R/W
b1
RTCF
Real-time clock periodic interrupt flag
R/W
b2
ALIE
Alarm interrupt enable bit
0: Alarm interrupt disabled
1: Alarm interrupt enabled
R/W
b3
ADJ30S 30-second adjustment bit
When 1 is written to this bit, the value of the
TRESEC register changes as follows.
When TRESEC register value
29: TRESEC 00
When TRESEC register value
30:
TRESEC
00, TREMIN TREMIN + 1
The read value is 0.
W
b4
RSTADJ Second counter reset adjustment bit
When 1 is written to this bit, the value of the
TRESEC register is set to 00 and the internal
counter is initialized.
The read value is 0.
W
b5
—
Nothing is assigned. The write value must be 0. The read value is 0.
—
b6
—
b7
TADJSF Correction status flag
0: No correction
1: Being corrected
R