R8C/38T-A Group
17. Timer RC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 326 of 730
Aug 05, 2011
17.6.5
Input Capture Function
The pulse width for the input capture signal must be at least three cycles of the timer RC operating clock.
The value of the TRCCNT register is transferred to the TRCGRi register after one or two cycles of the timer RC
operating clock after the input capture signal is input to the TRCIOi pin (i = A, B, C, or D) (when there is no
digital filter).
17.6.6
TRCMR Register in PWM2 Mode
When the CSTP bit in the TRCCR2 register is 1 (increment stops), do not set the TRCMR register when a
compare match occurs between registers TRCCNT and TRCGRA.
17.6.7
Count Source fHOCO
Count source fHOCO can be used within the power supply voltage range Vcc = 2.7 V to 5.5 V. At voltages
besides these, do not set bits CKS2 to CKS0 in the TRCCR1 register to 110b (fHOCO).
17.6.8
Module Standby
Write to the MSTTRC bit in the MSTCR register while the timer RC count is stopped. The timer RC module
standby bit exists in the MSTCR2 register.
17.6.9
Mode Switching
When switching modes during operation, set the CTS bit in the TRCMR register to 0 (count stops) before
switching.
After switching modes, set the flags in the TRCSR register to 0 and set the IR bit in the TRCIC register to 0
before starting operation.
For details, refer to 11.9.4 Changing Interrupt Sources.
17.6.10 Input Capture Operation when Count is Stopped
When the input capture function is used, if an input capture signal (edge selected by bits IOj0 and IOj1 (j = A or
B) in the TRCIOR0 register or bits IOk0 and IOk1 (k = C or D) in the TRCIOR1 register) is input to the
TRCIOi pin (i = A, B, C, or D), the IMFi bit in the TRCSR register is set to 1 even when the CTS bit in the
TRCMR register is set to 0 (count stops).