R8C/38T-A Group
22. Hardware LIN
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 530 of 730
Aug 05, 2011
Figure 22.3
Header Field Transmission Flowchart Example (1) (i = 0 or 1, x = 1 or 2)
Timer RJ
Set the Synch Break width
TRJ register
UART0 Set to transmit/receive mode
(8-bit transfer data length, internal clock, one-stop bit, parity disabled)
U0MR register
(1)
Timer RJ
Set the count source (f1, f2, f8, or fOCO)
Bits TCK0 to TCK2 in TRJMR register
(1, 2)
Hardware LIN
Set to master mode
MST bit in LINCT register
1
Hardware LIN
Set the LIN operation to start
LINE bit in LINCT register
1
Hardware LIN
Set interrupts to enabled
(Bus collision detection, Synch Break detection, Synch Field measurement)
Bits BCIE, SBIE, and SFIE in LINCT register
In master mode, the
Synch Field
measurement-
completed interrupt
cannot be used.
UART0 Set the BRG count source (f1, f8, or f32)
Bits CLK0 and CLK1 in U0C0 register
UART0 Set the bit rate
U0BRG register
Hardware LIN
Set the LIN operation to stop
LINE bit in LINCT register
0
Hardware LIN
Set bus collision detection to enabled
BCE bit in LINCR2 register
1
(1)
Hardware LIN
Clear the status flags
(Bus collision detection, Synch Break detection, Synch Field measurement)
Bits B2CLR, B1CLR, and B0CLR in LINST register
1
Notes:
1. When the previous communication completes normally and header field transmission is
performed again with the same settings, these settings can be omitted.
2. Although the timer-associated registers (TRJMR and TRJIOC) are set before the TRJ_0SR
register is set, there is no problem with this flow for the hardware LIN.
A
Timer RJ Assign the TRJIO_0 pin to the corresponding port
Setting of bits TRJIO_0SEL0 to TRJIO_0SEL2 in the TRJ_0SR register
UART0
Assign the RXD_i pin to the corresponding port
Setting of the RXD_0SEL bit in the U_0SR register
or bits RXD_1SEL0 and RXD_1SEL1 in the U_1SR register
INTx
Assign the INTx pin to the corresponding port
Setting of the INTSR0 register
(1, 2)
Timer RJ
Set to timer mode
Bits TMOD2 to TMOD0 in TRJMR register
000b
Timer RJ
Set the pulse output level from low to start
TEDGSEL bit in TRJIOC register
1
Set the count
source and TRJ
register as
appropriate for the
Synch Break period.
Set the BRG count
source and U0BRG
register as
appropriate for the
bit rate being used.
Set the hardware LIN
function to be selected
(the TIOSEL bit in the
TRJIOC register to 1).
If the wakeup function
is not necessary, the
setting of the INTx pin
can be omitted.
(1, 2)