R8C/38T-A Group
26. Flash Memory
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 626 of 730
Aug 05, 2011
26. Flash Memory
The flash memory supports the following three rewrite modes: CPU rewrite mode, standard serial I/O mode, and
parallel I/O mode.
26.1
Overview
The R8C/38T-A Group has on-chip data flash (1 KB × 4 blocks) with background operation (BGO) function.
Notes:
1. To perform programming or erasure, use VCC = 2.7 to 5.5 V as the supply voltage. Do not perform
programming or erasure at less than 2.7 V.
2. The number of blocks and block division vary with the MCU. Refer to Figure 26.1 for details.
3. Definition of program and erase endurance
The program and erase endurance is defined on a per-block basis. If the program and erase endurance is n (n
= 1,000 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to
different addresses in block A, a 1-Kbyte block, and then the block is erased, the program/erase endurance still
stands at one. When performing 100 or more rewrites, the actual erase count can be reduced by executing
program operations in such a way that all blank areas are used before performing an erase operation. Avoid
rewriting only particular blocks and try to average out the program and erase endurance of the blocks. It is also
advisable to retain data on the erase endurance of each block and limit the number of erase operations to a
certain number.
Table 26.1
Flash Memory Specifications
Item
Specification
Flash memory operating modes
3 modes (CPU rewrite, standard serial I/O, and parallel I/O)
Division of erase blocks
Programming method
Byte units/word units (program ROM area only)
Erasure method
Block erase
Programming and erasure control method
(1)Program and erase control by software commands
Rewrite protect
control method
Blocks 0 to 6
Rewrite protect control in block units by the lock bit
Blocks A, B, C, and D
(Data flash)
Individual rewrite protect control on blocks A, B, C, and D by bits
FMR14, FMR15, FMR16, and FMR17 in the FMR1 register
Number of commands
7 commands
Program and erase
Blocks 0 to 10
1,000 times
Blocks A, B, C, and D
(Data flash)
10,000 times
ID code check function
Standard serial I/O mode supported
ROM code protection
Parallel I/O mode supported
Table 26.2
Flash Memory Rewrite Mode
Flash Memory
Rewrite Mode
CPU Rewrite Mode
Standard Serial I/O Mode
Parallel I/O Mode
Function
User ROM area is rewritten by
executing software commands from
the CPU.
User ROM area is rewritten
using a dedicated serial
programmer.
User ROM area is
rewritten using a
dedicated parallel
programmer.
Rewritable area
User ROM
Rewrite programs
User program
Standard boot program
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