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R8C/38T-A Group
17. Timer RC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 313 of 730
Aug 05, 2011
17.4
Selectable Functions
17.4.1
Input Digital Filter for Input Capture
can be latched internally through the digital filter circuit. This circuit consists of three cascaded latch circuits
and a match detection circuit. When the TRCIOA to TRCIOD and TRCTRG input are sampled on the clock
selected by bits DFCK0 and DFCK1 in the TRCDF register and three outputs from the latch circuits match, the
level is passed forward to the next circuit. If they do not match, the previous level is retained. That is, the pulse
input with a width of three sampling clocks or more is recognized as a signal. If not, the change in the signal is
recognized as noise and cancelled.
Do not use the digital filter immediately after a reset. Wait for four cycles of the sampling clock and make the
setting for input capture before using the input capture function.
Figure 17.19
Digital Filter Circuit Block Diagram
TRCIOA to
TRCIOD or
TRCTRG input
Sampling clock
selection
circuit
Edge
detection
circuit
Match
detection
circuit
C
DQ
Latch
C
DQ
Latch
C
DQ
Latch
C
DQ
Latch
DFTRG
DFA to DFD
IOA0 and IOA1
IOD0 and IOD1
f1 or fHOCO
f32
TRCCLK
f8
f4
f2
f1
f32
f8
CKS0 to CKS2
DFCK0 and DFCK1
C
DQ
Latch
CKS0 to CKS2: Bits in TRCCR1 register
IOA0 and IOA1: Bits in TRCIOR0 register
IOD0 and IOD1: Bits in TRCIOR1 register
DFA to DFD, DFTRG, DFCK0, DFCK1: Bits in TRCDF register
If the level does not match three
times, it is assumed to be noise
and not transmitted
Signal transmission
delayed up to five
sampling clocks
Clock period selected by
CKS0 to CKS2 or DFCK0 and DFCK1
Sampling clock
TRCIOA to
TRCIOD or
TRCTRG input
Input after passing
through digital filter
Timer RC operating clock
fHOCO-F
fHOCO