R8C/38T-A Group
10. Power Control
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 123 of 730
Aug 05, 2011
10.5.3
Exiting Stop Mode
A reset or a peripheral function interrupt is used to exit stop mode.
To use a peripheral function interrupt to exit stop mode, the following items must be set before setting the
CM10 bit in the CM1 register to 1:
(1) Set the interrupt priority level in bits ILVL0 to ILVL2 in the interrupt priority level registers for the
peripheral function interrupts that are used to exit stop mode.
Also, set 000b (interrupt disabled) in bits ILVL0 to ILVL2 in the interrupt priority level registers for the
peripheral function interrupts that are not to be used to exit stop mode.
(2) Operate the peripheral functions to be used to exit stop mode.
(3) Set the I flag in the FLG register to 1.
When a peripheral function interrupt is used to exit stop mode, the interrupt sequence is executed after the
interrupt request is generated and the supply of the CPU clock starts.
The CPU clock when a peripheral function interrupt is used to exit stop mode is a divide-by-8 of the clock used
immediately before entering stop mode. When entering stop mode, set the CM35 bit in the CM3 register to 0
(settings of CM06 bit in CM0 register and bits CM16 and CM17 in CM1 register enabled).
Figure 10.4
Time from Stop Mode to Interrupt Routine Execution
The total of T0 to T4
amounts to the time
from stop mode to
interrupt routine
execution.
Remarks
Oscillation time of CPU clock
source used immediately
before stop mode
Stop
mode
Internal power
stabilization
time
T1
T0
100
s (max.)
Interrupt request generated
0
(flash memory operates)
1
(flash memory stops)
FMSTP Bit
FMR0 Register
Period of CPU clock
2 cycles
Same as above
Time until
CPU Clock
Supply (T3)
CPU clock
restart sequence
T3
Period of CPU clock
20 cycles
Same as above
Time for
Interrupt
Sequence (T4)
Interrupt
sequence
T4
Time until
Flash Memory
Activation (T2)
T2
Period of system clock
1 cycle + 60 s (max.)
Period of system clock
1 cycle
Flash memory
activation sequence
Internal Power
Stabilization Time
(T0)
100
s (max.)
100
s (max.)