R8C/38T-A Group
13. DTC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 180 of 730
Aug 05, 2011
13.3.5
Repeat Mode
One to 255 bytes of data are transferred by one activation. Either the transfer source or destination should be
specified as the repeat area. The number of transfer times can be 1 to 255. On completion of the specified
number of transfer times, the DTCCTj (i =0 to 23) register and the address specified for the repeat area are
initialized to continue transfers. When the data transfer causing the DTCCTj register value to change to 0 is
performed while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled), an interrupt request
for the CPU is generated during DTC operation.
The lower 8 bits of the initial value for the repeat area address must be 00h. The size of data to be transferred
must be set to 255 bytes or less before the specified number of transfer times is completed.
j =0 to 23
Figure 13.9
Data Transfers in Repeat Mode (j = 0 to 23)
Table 13.10
Register Functions in Repeat Mode
Register
Symbol
Function
DTC block size register j
DTBLSj
Size of the data block to be transferred by one activation
DTC transfer count register j
DTCCTj
Number of times of data transfers
DTC transfer count reload register j DTRLDj
This register value is reloaded to the DTCCT register
(Data transfer count is initialized)
DTC source address register j
DTSARj
Data transfer source address
DTC destination address register j
DTDARj
Data transfer destination address
SRC
Transfer
DST
Transfer source
Transfer destination
Size of the data block to be transferred by
one activation (N bytes)
DTBLSj = N
DTCCTj
≠ 1
DTSARj = SRC
DTDARj = DST
Bits b3 to b0 in
DTCCR register
0X11b
1X11b
X001b
X101b
Source address
control
Repeat area
Fixed
Incremented
Destination address
control
Fixed
Incremented
Repeat area
Source address
after transfer
SRC + N
SRC
SRC + N
Destination address
after transfer
DST
DST + N
DTCCTj register = 1
SRC0/DST0
Repeat area
Bits b3 to b0 in
DTCCR register
0X11b
1X11b
X001b
X101b
Source address
control
Repeat area
Fixed
Incremented
Destination address
control
Fixed
Incremented
Repeat area
Source address
after transfer
SRC0
SRC
SRC + N
Destination address
after transfer
DST
DST + N
DST0
SRC/DST
Address of the repeat area is initialized
after a transfer.
DTBLSj = N
DTCCTj = 1
DTSARj = SRC
DTDARj = DST
SRC0: Initial source address value
DST0: Initial destination address value
X: 0 or 1
DTCCTj register
≠ 1