R8C/38T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 490 of 730
Aug 05, 2011
21.3.3.1
Initialization in 4-Wire Bus Communication Mode
set the TE_NAKIE bit in the SIER register to 0 (transmission disabled) and the RE_STIE bit to 0 (reception
disabled) for initialization.
To change the communication mode or the communication format, set the TE_NAKIE bit to 0 and the
RE_STIE bit to 0 before making the change.
Even if the RE_STIE bit is set to 0, the contents of bits RDRF and ORER_AL and the SIRDR register are
retained.
After slave receive operation, SCS may be asserted when the mode is switched to master mode even though no
transfer start condition is written.
Figure 21.13
Initialization in 4-Wire Bus Communication Mode
Start
SIMR2 register
MS bit
1
SICR1 register
Set bits CKS0 to CKS2
Set RCVD bit
SISR register
ORER_AL bit
0 (1)
SIER register
RE_STIE bit
1 (receive)
TE_NAKIE bit
1 (transmit)
Set bits RIE, TEIE, and TIE
End
Note:
1. To set the ORER_AL bit to 0, write 0 after reading it as 1.
SIER register
RE_STIE bit
0
TE_NAKIE bit
0
SICR1 register
Set MST bit
SIMR1 register
Set CPHS bit
Set CPOS_WAIT bit
MLS bit
0
Reception disabled
Transmission disabled
SSBR register
Set bits BS0 to BS3
SSU data transfer length setting
Mode selected (4-wire system communication mode)
Clock phase selected (data change at odd/even edge)
Clock state selected (high/low when clock stops)
MSB first selected
Master/slave mode selected
SSCK pin selected (port function)
SSCK pin open-drain output selected
SCS pin I/O setting
Bidirectional mode setting
Clock period setting
Receive disable bit setting
Overrun error flag cleared
Transmission/reception enable setting
Interrupt enable setting
SIMR2 register
SCKS bit
1
Set bits SOOS, CSS0, CSS1,
and BIDE