R8C/38T-A Group
19. Serial Interface (UART0)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 380 of 730
Aug 05, 2011
19.2
Registers
X: Undefined
Note:
1. For details on access, refer to the description of the individual registers.
19.2.1
UART0 Transmit/Receive Mode Register (U0MR)
Note:
1. The PRY bit is enabled when the PRTYE bit is 1 (parity enabled).
Table 19.3
UART0 Register Configuration
Register Name
Symbol
After Reset
Address
Access Size
UART0_0 Transmit/Receive Mode Register
U0MR_0
00h
00080h
8
UART0_0 Bit Rate Register
U0BRG_0
XXh
00081h
8
UART0_0 Transmit Buffer Register
U0TB_0
XXh
00082h
XXh
00083h
UART0_0 Transmit/Receive Control Register 0
U0C0_0
00001000b
00084h
8
UART0_0 Transmit/Receive Control Register 1
U0C1_0
00000010b
00085h
8
UART0_0 Receive Buffer Register
U0RB_0
XXXXh
00086h
UART0_0 Interrupt Flag and Enable Register
U0IR_0
00h
00088h
8
UART0_1 Transmit/Receive Mode Register
U0MR_1
00h
00090h
8
UART0_1 Bit Rate Register
U0BRG_1
XXh
00091h
8
UART0_1 Transmit Buffer Register
U0TB_1
XXh
00092h
XXh
00093h
UART0_1 Transmit/Receive Control Register 0
U0C0_1
00001000b
00094h
8
UART0_1 Transmit/Receive Control Register 1
U0C1_1
00000010b
00095h
8
UART0_1 Receive Buffer Register
U0RB_1
XXXXh
00096h
UART0_1 Interrupt Flag and Enable Register
U0IR_1
00h
00098h
8
Address 00080h (U0MR_0), 00090h (U0MR_1)
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
000
0000
Bit
Symbol
Bit Name
Function
R/W
b0
SMD0
Serial I/O mode select bits
b2 b1 b0
0 0 0: Serial interface disabled (operation
stopped)
0 0 1: Clock synchronous serial I/O mode
1 0 0: UART mode, transfer data 7 bits long
1 0 1: UART mode, transfer data 8 bits long
1 1 0: UART mode, transfer data 9 bits long
Other than the above: Do not set.
R/W
b1
SMD1
R/W
b2
SMD2
R/W
b3
CKDIR
Internal/external clock select bit
0: Internal clock
1: External clock
R/W
b4
STPS
Stop bit length select bit
0: One stop bit
1: Two stop bits
R/W
b5
PRY
Odd/even parity select bit
(1)0: Odd parity
1: Even parity
R/W
b6
PRYE
Parity enable bit
0: Parity disabled
1: Parity enabled
R/W
b7
—
Reserved
Set to 0.
R/W