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R8C/38T-A Group
18. Timer RE2
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 333 of 730
Aug 05, 2011
18.2.3
Timer RE2 Compare Data Register (TREMIN)
in Compare Match Timer Mode
The TREMIN register is always compared with the TRESEC register, and the CMIF bit in the TREIFR register
is set to 1 (interrupt requested) when the values of both the registers match. When the CMIE bit in the TREIER
register is 1 (compare match interrupt enabled), an interrupt request is generated.
Write to the TREMIN register when the RUN bit in the TRECR register is 0 (count stops).
18.2.4
Timer RE2 Minute Data Register (TREMIN) in Real-Time Clock Mode
Set the PROTECT bit in the TREPRC register to 1 (write enabled) before rewriting the TREMIN register.
Set values from 00 to 59 by the BCD code.
When the digit increments from the TRESEC register, 1 is added.
Read or write to these bits when the BSY bit in the TRESEC register is 0 (data not being updated).
Address 00171h
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
000
0000
After reset by
RTCRST bit in
TRECR register
0
000
0000
Bit
Symbol
Bit Name
Function
R/W
b0
MN0
Compare data bit 0
The 8-bit compare data is stored.
Write the compare value.
R/W
b1
MN1
Compare data bit 1
R/W
b2
MN2
Compare data bit 2
R/W
b3
MN3
Compare data bit 3
R/W
b4
MN4
Compare data bit 4
R/W
b5
MN5
Compare data bit 5
R/W
b6
MN6
Compare data bit 6
R/W
b7
MN7
Compare data bit 7
R/W
Address 00171h
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
000
0000
After reset by
RTCRST bit in
TRECR register
0
000
0000
Bit
Symbol
Bit Name
Function
Setting Range
R/W
b0
MN00
First digit of minute count bits
Count from 0 to 9 every minute.
When the digit increments, 1 is
added to the second digit of
minutes.
0 to 9 (BCD code)
R/W
b1
MN01
R/W
b2
MN02
R/W
b3
MN03
R/W
b4
MN10
Second digit of minute count bits
When counting from 0 to 5, 60
minutes are counted.
0 to 5 (BCD code)
R/W
b5
MN11
R/W
b6
MN12
R/W
b7
MN7
Set to 0.
R/W